Abstract: A source electrode Vdd is formed in a region between a field PMOS 1 and a field PMOS 2 as high side switches of a latch circuit. This latch circuit is utilized in the state where a lower side of one of the two high side switches is completely depleted. Field PMOS 1 and field PMOS 2 share a P+-type impurity diffusion region, an N+-type impurity diffusion region and a P+-type impurity diffusion region, which are connected to source electrode Vdd. It is therefore possible to provide a semiconductor device capable of reducing the area thereof in the direction parallel to the main surface of a semiconductor substrate.

Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

Abstract: A semiconductor circuit is provided which has a high breakdown voltage and is capable of outputting a large current. Field transistors (Q1, Q11) are cross-coupled. The gate of the first field transistor (Q1) and the drain of the second field transistor (Q11) are not directly connected to the drain of an MOS transistor (Q4) but are connected to the base of a bipolar transistor (Q12). The second field transistor (Q11) has its source connected to the collector of the bipolar transistor (Q12) and the MOS transistor (Q4) has its drain connected to the emitter of the bipolar transistor (Q12). When the current amplification factor of the bipolar transistor (Q12) is taken as &bgr;, then the current of the output (SO) can be increased approximately &bgr; times.

Abstract: A high resistance n-type base layer is formed on a silicon substrate with an insulating layer made of a silicon oxide film therebetween. In the high resistance n-type base layer a p-ch MOS transistor is formed. The p-ch MOS transistor is electrically isolated from another element by trench isolation formed of a trench. A p+ source layer in the p-ch MOS transistor surrounds a periphery of a p+ drain layer and has, for example, an elliptical planar configuration. A semiconductor device thus formed has a high drive capacity and is suitable to high integration.

Abstract: A semiconductor device includes an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N− epi layer, which constitutes a device formation region, and an N− epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N− epi layer (invalid area) to the P+ diffusion layer. Since the potential of the N− epi layer (invalid area) can be made equal to that of the P+ diffusion layer, it is possible to prevent the electron supply from the P+ diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.

Abstract: A DMOS transistor in which a main current flows between first and second main surfaces of a silicon substrate is formed. DMOS transistor has a p-type diffusion region formed in the first main surface, an n+ diffusion region formed in the first main surface in p-type diffusion region, and a gate electrode facing p-type diffusion region sandwiched between n+ diffusion region and n− layer via a gate insulating layer. A dielectric layer is formed in the silicon substrate so as to be adjacent to n− layer, and made of a material having a dielectric constant higher than that of silicon. Therefore, the semiconductor device which can be easily formed while suppressing increase in process cost and has an improved trade-off (effective on-state resistance) between a withstand voltage and on-state resistance by generating an electric field almost uniform in the direction of the thickness of a semiconductor substrate can be attained.

Abstract: A semiconductor device of the present invention comprises: an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N− epi layer, which constitutes a device formation region, and an N− epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N− epi layer (invalid area) to the P+ diffusion layer. Since the potential of the N− epi layer (invalid area) can be made equal to that of the P+ diffusion layer, it is possible to prevent the electron supply from the P+ diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.

Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer. Thus, a high breakdown voltage semiconductor device and a manufacturing process therefor is provided, which includes a low breakdown voltage element region and a high breakdown voltage element region, and a high breakdown isolation region separates a high breakdown voltage region without impairing the characteristics of an element formed on the low breakdown voltage element region.

Abstract: A semiconductor device includes a semiconductor layer having a main surface (100a), a first region (101) of a first conductivity type, a second region (102) of a second conductivity type, and a third region (103) of the second conductivity type, the first region (101) and the second region (102) having a first boundary (101a) formed therebetween, the first boundary (101a) being perpendicular to the main surface (100a), the third region (103) being formed in the first region (101) in spaced apart relation to the second region (102), the third region (103) having a depth less than the depth of the first boundary (101a) from the main surface (100a); and a control electrode (201) insulated from and overlying the main surface (100a) and extending from the first boundary (101a) to a second boundary (101b) formed between the first region (101) and the third region (103). The semiconductor device improves a tradeoff between breakdown voltage and on-resistance.

Abstract: A semiconductor device includes a p type semiconductor substrate, a first n type region formed at the semiconductor substrate, a first n channel DMOS transistor formed in the first n type region, a second n type region formed at the semiconductor substrate, a vertical type pnp bipolar transistor formed in the second n type region, and a second n channel DMOS transistor formed in the second n type region. The first n channel DMOS transistor has a drain for receiving a high power supply voltage (Vdc) and a source for supplying an output voltage (Vout). The bipolar transistor has a base connected to the gate of the first n channel DMOS transistor, an emitter connected to the source of the first n channel DMOS transistor, and a collector connected to the ground. The second n channel DMOS transistor has a drain connected to the gate of the first n channel DMOS transistor and a source connected to the ground.

Abstract: A semiconductor circuit is provided which has a high breakdown voltage and is capable of outputting a large current. Field transistors (Q1, Q11) are cross-coupled. The gate of the first field transistor (Q1) and the drain of the second field transistor (Q11) are not directly connected to the drain of an MOS transistor (Q4) but are connected to the base of a bipolar transistor (Q12). The second field transistor (Q11) has its source connected to the collector of the bipolar transistor (Q12) and the MOS transistor (Q4) has its drain connected to the emitter of the bipolar transistor (Q12). When the current amplification factor of the bipolar transistor (Q12) is taken as &bgr;, then the current of the output (SO) can be increased approximately &bgr; times.

Abstract: A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.

Abstract: The method for manufacturing a semiconductor device includes the steps of: removing an oxide film in a region including a fuse region at the formation of an opening for the formation of a vertical interconnection in an oxide film serving as an upper insulating layer; and forming the vertical interconnection for electrically connecting interconnection layers below and above the oxide film and the interconnection layer placed on an upper side of the oxide film as one upper conductive layer at the same time.

Abstract: The main purpose is to provide a semiconductor device which has a field plate wherein the electric field concentration at a step part can be eliminated and a higher withstanding voltage can be gained. A field plate is provided on a substrate. The field plate has a step part which bends toward the downward direction from the surface of the substrate.

Abstract: A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.

Abstract: A DMOS transistor in which a main current flows between first and second main surfaces of a silicon substrate is formed. DMOS transistor has a p-type diffusion region formed in the first main surface, an n+ diffusion region formed in the first main surface in p-type diffusion region, and a gate electrode facing p-type diffusion region sandwiched between n+ diffusion region and n− layer via a gate insulating layer. A dielectric layer is formed in the silicon substrate so as to be adjacent to n− layer, and made of a material having a dielectric constant higher than that of silicon. Therefore, the semiconductor device which can be easily formed while suppressing increase in process cost and has an improved trade-off (effective on-state resistance) between a withstand voltage and on-state resistance by generating an electric field almost uniform in the direction of the thickness of a semiconductor substrate can be attained.

Abstract: A field MOS transistor having a high withstand voltage is disclosed. An island region of an epitaxial layer is surrounded by a heavily-doped isolation layer and a lightly-doped isolation layer formed thereon. A channel region is formed in the island region so as to assume the same doping level as that of the lightly-doped isolation layer. A region is formed below the island region so as to assume the same doping level as that of the heavily-doped isolation layer, thus supplying a back gate voltage to the transistor. The channel formation region is formed simultaneously with formation of the lightly-doped isolation layer, and the region below the island region is formed simultaneously with the heavily-doped isolation layer. As a result, manufacturing processes can be simplified.

Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer.

Abstract: A field MOS transistor having a high withstand voltage is disclosed. An island region of an epitaxial layer is surrounded by a heavily-doped isolation layer and a lightly-doped isolation layer formed thereon. A channel region is formed in the island region so as to assume the same doping level as that of the lightly-doped isolation layer. A region is formed below the island region so as to assume the same doping level as that of the heavily-doped isolation layer, thus supplying a back gate voltage to the transistor. The channel formation region is formed simultaneously with formation of the lightly-doped isolation layer, and the region below the island region is formed simultaneously with the heavily-doped isolation layer. As a result, manufacturing processes can be simplified.

Abstract: An N+ buried diffusion region is formed between a P− silicon substrate and an N− epitaxial layer and a P+ buried diffusion region is formed between the N+ buried diffusion region and the N− epitaxial layer. An N diffusion region, a P diffusion region and an N diffusion region are formed in the surface for the N− epitaxial layer. The surface of the P+ buried diffusion region located, approximately, beneath the N diffusion region is recessed so as to go far away from the N diffusion region and a narrowed part is formed in this part. Thereby, in the OFF condition, the depletion layer further extends in the part where the narrowed part is formed. As a result, the withstanding voltage of the semiconductor device is increased.