Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.

Abstract: A semiconductor device includes a plurality of floating regions, an insulating layer and a capacitance forming portion. The plurality of floating regions are arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween. The plurality of floating regions include a first floating region and a second floating region. The second floating region is located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate. The insulating layer is interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate. The capacitance forming portion forms an external capacitance in parallel with the capacitance of the insulating region between the first floating region and the island region of the predetermined potential.

Abstract: On a main surface of a semiconductor substrate, an N? semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N? semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N? semiconductor layer. In a predetermined region of the N? semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N? semiconductor layer is formed from the surface of the N? semiconductor layer to the dielectric portion.

Abstract: The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics.

Abstract: A voltage mitigating element mitigating a voltage applied across a gate insulating film in an off state of an insulated gate bipolar transistor (IGBT) is arranged to a gate electrode node of a P-channel MOS transistor provided for suppressing flow-in of holes at the time of turn-off of the IGBT. Withstanding voltage characteristics are improved and an occupation area thereof is reduced while maintaining switching characteristics and a low on-resistance of an insulated gate bipolar transistor.

Abstract: The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintainingcharacteristics.

Abstract: The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics.

Abstract: A semiconductor layer provided on a BOX (buried oxide) layer includes a first P-type region, an N+-type region, and an N?-type region which together form a diode. A plurality of second P-type regions are provided on a bottom part of the semiconductor layer. A plurality of insulating oxide films are interposed between the plurality of second P-type regions. When the diode is in a reverse-biased state, the second P-type region directly below the N+-type region is approximately the same in potential as the N+-type region. The second P-type region will be lower in potential relative to this second P-type region directly below the N+-type region, as the second P-type region gets nearer to the first P-type region. Electric field concentration can thus be relaxed at an interface between the semiconductor layer and the BOX layer, whereby improvement in breakdown voltage of the diode is realized.

Abstract: An n? type semiconductor region is provided with an n? diffusion region serving as a drain region, and at one side of the n? diffusion region a p diffusion region and an n+ diffusion region serving as a source region are provided. At an other side of the n? diffusion region a trench is provided and has an insulator introduced therein. Immediately under the n? diffusion region a p? buried layer is provided. In a region of the n? semiconductor region an n+ diffusion region to which a high potential is applied is provided and electrically connected to the n? diffusion region by an interconnect having a resistor. On a surface of a portion of the p diffusion region that is sandwiched between the n+ diffusion region and the n? diffusion region a gate electrode is provided, with a gate insulation film posed therebetween.

Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.

Abstract: A semiconductor device has a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region and a second conductivity-type third semiconductor region both located on or above the first semiconductor region, a second conductivity-type fourth semiconductor region between the second semiconductor region and the third semiconductor region, and a first conductivity-type fifth semiconductor region between the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region and the fifth semiconductor region are electrically connected by a conductive member. A distance between the fourth semiconductor region and the third semiconductor region is larger than a width of the fourth semiconductor region.

Abstract: The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics.

Abstract: A semiconductor device includes a P diffusion region formed in the surface of an N? epitaxial layer apart from other P diffusion regions; an N+ diffusion region formed in the surface of the P diffusion region so as to be surrounded by the P diffusion region; a second collector electrode provided on the N+ diffusion region and connected to a first collector electrode; and an electrode provided on and extending through the P diffusion region and the N? epitaxial layer to form a conducting path from the N? epitaxial layer to the P diffusion region. This semiconductor device can improve both the operation and the reverse conducting capability of an IGBT.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

Abstract: A voltage mitigating element mitigating a voltage applied across a gate insulating film in an off state of an insulated gate bipolar transistor (IGBT) is arranged to a gate electrode node of a P-channel MOS transistor provided for suppressing flow-in of holes at the time of turn-off of the IGBT. Withstanding voltage characteristics are improved and an occupation area thereof is reduced while maintaining switching characteristics and a low on-resistance of an insulated gate bipolar transistor.

Abstract: A semiconductor layer of n? type is formed on a semiconductor substrate of p? type. A first buried impurity region of n+ type is formed at an interface between the semiconductor substrate and the semiconductor layer. A second buried impurity region of p+ type is formed at an interface between the first buried impurity region and the semiconductor layer. Above the first and second buried impurity regions, a first impurity region of n type is formed in an upper surface of the semiconductor layer. Above the first and second buried impurity regions, a second impurity region of p type is also formed apart from the first impurity region in the upper surface of the semiconductor layer. When the second impurity region becomes higher in potential than the first impurity region, the second impurity region and the second buried impurity region are electrically isolated from each other by a depletion layer.

Abstract: A semiconductor device that can prevent an unnecessary current path from being formed so that a normal signal is transmitted is provided. The semiconductor device comprises an N? region formed in a surface region of a P type substrate, a P region formed in the surface region, the P region included in the N? region or adjacent to the N? region, one or more semiconductor elements each of which has a first N type region and a second N type region formed in a portion of the P region, the first N type region and the second N type region being separated from each other, a first electrode formed on the first N type region, a second electrode formed on the second N type region, and a gate electrode formed over a surface of the P region between the first N type region and the second N type region. The first N type region and the second N type region are surrounded by the P region and separated from the N? region.

Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.

Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.