Abstract: A semiconductor layer provided on a BOX (buried oxide) layer includes a first P-type region, an N+-type region, and an N?-type region which together form a diode. A plurality of second P-type regions are provided on a bottom part of the semiconductor layer. A plurality of insulating oxide films are interposed between the plurality of second P-type regions. When the diode is in a reverse-biased state, the second P-type region directly below the N+-type region is approximately the same in potential as the N+-type region. The second P-type region will be lower in potential relative to this second P-type region directly below the N+-type region, as the second P-type region gets nearer to the first P-type region. Electric field concentration can thus be relaxed at an interface between the semiconductor layer and the BOX layer, whereby improvement in breakdown voltage of the diode is realized.

Abstract: An n? type semiconductor region is provided with an n? diffusion region serving as a drain region, and at one side of the n? diffusion region a p diffusion region and an n+ diffusion region serving as a source region are provided. At an other side of the n? diffusion region a trench is provided and has an insulator introduced therein. Immediately under the n? diffusion region a p? buried layer is provided. In a region of the n? semiconductor region an n+ diffusion region to which a high potential is applied is provided and electrically connected to the n? diffusion region by an interconnect having a resistor. On a surface of a portion of the p diffusion region that is sandwiched between the n+ diffusion region and the n? diffusion region a gate electrode is provided, with a gate insulation film posed therebetween.

Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.

Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.

Abstract: A semiconductor device has a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region and a second conductivity-type third semiconductor region both located on or above the first semiconductor region, a second conductivity-type fourth semiconductor region between the second semiconductor region and the third semiconductor region, and a first conductivity-type fifth semiconductor region between the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region and the fifth semiconductor region are electrically connected by a conductive member. A distance between the fourth semiconductor region and the third semiconductor region is larger than a width of the fourth semiconductor region.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

Abstract: A semiconductor device that can prevent an unnecessary current path from being formed so that a normal signal is transmitted is provided. The semiconductor device comprises an N? region formed in a surface region of a P type substrate, a P region formed in the surface region, the P region included in the N? region or adjacent to the N? region, one or more semiconductor elements each of which has a first N type region and a second N type region formed in a portion of the P region, the first N type region and the second N type region being separated from each other, a first electrode formed on the first N type region, a second electrode formed on the second N type region, and a gate electrode formed over a surface of the P region between the first N type region and the second N type region. The first N type region and the second N type region are surrounded by the P region and separated from the N? region.

Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

Abstract: A PMOS transistor (Q2) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region (5), a P diffusion region (6), and a conductive film (10) and a second gate electrode (15) provided via a gate oxide film (21) on a surface of an N? epitaxial layer (2) between the P diffusion regions (5 and 6). The gate oxide film (21) is formed in a thickness having a gate breakdown voltage higher than the element breakdown voltage of a typical field oxide film and the like.

Abstract: A semiconductor layer of n? type is formed on a semiconductor substrate of p? type. A first buried impurity region of n+ type is formed at an interface between the semiconductor substrate and the semiconductor layer. A second buried impurity region of p+ type is formed at an interface between the first buried impurity region and the semiconductor layer. Above the first and second buried impurity regions, a first impurity region of n type is formed in an upper surface of the semiconductor layer. Above the first and second buried impurity regions, a second impurity region of p type is also formed apart from the first impurity region in the upper surface of the semiconductor layer. When the second impurity region becomes higher in potential than the first impurity region, the second impurity region and the second buried impurity region are electrically isolated from each other by a depletion layer.

Abstract: A semiconductor device includes a P diffusion region formed in the surface of an N? epitaxial layer apart from other P diffusion regions; an N+ diffusion region formed in the surface of the P diffusion region so as to be surrounded by the P diffusion region; a second collector electrode provided on the N+ diffusion region and connected to a first collector electrode; and an electrode provided on and extending through the P diffusion region and the N? epitaxial layer to form a conducting path from the N? epitaxial layer to the P diffusion region. This semiconductor device can improve both the operation and the reverse conducting capability of an IGBT.

Abstract: A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N?-type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.

Abstract: A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N?type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.

Abstract: An N+ buried diffusion region is formed between a P? silicon substrate and an N? epitaxial layer and a P+ buried diffusion region is formed between the N+ buried diffusion region and the N? epitaxial layer. An N diffusion region, a P diffusion region and an N diffusion region are formed in the surface for the N? epitaxial layer. The surface of the P+ buried diffusion region located, approximately, beneath the N diffusion region is recessed so as to go far away from the N diffusion region and a narrowed part is formed in this part. Thereby, in the OFF condition, the depletion layer further extends in the part where the narrowed part is formed. As a result, the withstanding voltage of the semiconductor device is increased.

Abstract: N+-type diffusion regions, P-type diffusion region and others are formed at and near a surface of an N?-type epitaxial layer on a p-type silicon substrate. Gate electrode portions are formed on P-type diffusion region located between N?-type diffusion regions and N?-type epitaxial layer with a gate insulating film therebetween. A source electrode and a drain electrode are formed. Under a field isolating film, a P-type diffusion region is formed discretely in a direction crossing a direction of a current flow in the on state. Thereby, such a semiconductor device is obtained that rising of an on resistance can be suppressed in an on state while keeping an effect of reducing an electric field.

Abstract: A PMOS transistor (Q2) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region (5), a P diffusion region (6), and a conductive film (10) and a second gate electrode (15) provided via a gate oxide film (21) on a surface of an N? epitaxial layer (2) between the P diffusion regions (5 and 6). The gate oxide film (21) is formed in a thickness having a gate breakdown voltage higher than the element breakdown voltage of a typical field oxide film and the like.

Abstract: A source electrode Vdd is formed in a region between a field PMOS 1 and a field PMOS 2 as high side switches of a latch circuit. This latch circuit is utilized in the state where a lower side of one of the two high side switches is completely depleted. Field PMOS 1 and field PMOS 2 share a P+-type impurity diffusion region, an N+-type impurity diffusion region and a P+-type impurity diffusion region, which are connected to source electrode Vdd. It is therefore possible to provide a semiconductor device capable of reducing the area thereof in the direction parallel to the main surface of a semiconductor substrate.

Abstract: An n-type well is formed in a p?-type semiconductor substrate and a p?-type epitaxial layer is formed on; the n-type well. An n?-type well is formed in the, p-type epitaxial layer on the n-type well so as to allow a RESURF operation. A p-type island is formed in the n?-type well at a position above the n-type well to form an island region for high withstand-voltage separation. Thus, the withstand voltage of the separated island is improved.

Abstract: A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N−type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.