Abstract: A P.sup.+ layer (3) and an N.sup.+ layer (1) are provided on the top and bottom surfaces of an N.sup.- layer (21), respectively. An electrode (7) is formed on the P.sup.+ layer (3), while an electrode (8) is formed on the bottom surface of the N.sup.+ layer (1). In a direction from the electrode (7) to the electrode (8), the area of the cross section of the N.sup.- layer (21) is decreased, which cross section is perpendicular to the direction. An N.sup.-- layer (22) is formed complementarily to the N.sup.- layer (21) which is decreased in cross-sectional area. When a potential applied to the electrode (8) is higher than a potential applied to the electrode (7), a depletion layer extends from a PN junction formed by the P.sup.+ layer (3) and the N.sup.- layer (21). Since the impurity concentration of the N.sup.- layer ( 21) is lower than that of the P.sup.+ layer (3), the depletion layer extends substantially to the N.sup.- layer (21). The depletion layer extending to the N.sup.

Abstract: A thyristor structure comprises a p.sup.+ -type substrate (21), an n-type base layer (22), a first p-type diffusion region (23) and an n.sup.+ -type diffusion region (25). A MOS structure comprises the base layer (22), first and second p-type diffusion regions (23, 24) and the n.sup.+ -type diffusion region (25). A positive voltage is applied to a gate electrode (27) to form a channel in a portion of the first diffusion region (23) just under the gate electrode (27), so that a cathode electrode (28) supplies carriers to the base layer (22) through the n.sup.+ -type diffusion region (25) and the channel, to turn on the thyristor. A negative voltage is applied to the gate electrode (27) to form a channel in a portion of the base layer (22) just under the gate electrode (27), so that the first p-type diffusion region (23) and the n.sup.+ -type diffusion region (25) are shorted through the channel, the second p-type diffusion region (24) and the cathode electrode (28), to turn off the thyristor.

Abstract: First and second semiconductor elements are formed in first and second semiconductor element forming regions which have the same thickness, include first and second semiconductor layers and are separated with dielectric isolation from each other. The thickness of the first semiconductor layer is made different between the first and second semiconductor element forming regions, so that the thickness of the second semiconductor layer becomes different between the first and second semiconductor element forming regions. Thus, the semiconductor device may have the semiconductor elements which have second semiconductor layers with different thicknesses in accordance with desired electrical characteristics for each of the semiconductor elements formed in the first and second semiconductor element forming regions, to complement a semiconductor device having the semiconductor elements each of which has independent optimum electrical characteristics.

Abstract: A thyristor of the present invention turns on by applying a specified voltage to a first control electrode and turns off by applying a specified voltage to a second control electrode. These first and second control electrodes are independent of each other, so that the turning-on and turning-off conditions can be determined independently. When a transistor having the second control electrode is turned on by applying the specified voltage to the second control electrode until just before the turning-on, a first main electrode and a first semiconductor region can be electrically connected, so that the back gate potential of the transistor having the first control electrode can be fixed at the potential of the first main electrode.

Abstract: An n.sup.+ -type diffusion region (19) is formed in a surface of an n.sup.- -type semiconductor island (11) corresponding to a protrusion (23) by selective diffusion so that the bottom thereof is in contact with an n.sup.+ -type semiconductor layer (12) surrounding the island (11). A drain electrode (22) is formed on the diffusion region (19) to extract an operating current of a VDMOS transistor flowing through the n.sup.+ -type semiconductor layer (12). By virtue of the protrusion (23), the diffusion region (19) can reach the n.sup.+ -type semiconductor layer (12) by not so deep diffusion. Thus, lateral diffusion can be suppressed so that an area required for the diffusion region (19) may be smaller.

Abstract: A semiconductor device chip holder which has a plurality of plates laminated together, each having a different thermal expansion coefficient. A semiconductor chip is mounted on the upper surface of the chip holder, and molding resin is disposed only on the upper side of the chip holder encapsulating the semiconductor chip. At high temperatures the bimetal effect due to this construction causes the chip holder to warp, which generates a stress acting on the semiconductor chip compressing it. The piezoresistance effect thus obtained reduces the on-resistance of the semiconductor chip, thereby enabling the device to exhibit a stable and low on-resistance over a wide temperature range.