Abstract: A high-breakdown voltage semiconductor device and a fabrication method are disclosed. A dielectric layer dielectrically isolates a semiconductor substrate from an n.sup.- type semiconductor layer. An n.sup.+ type semiconductor region having a lower resistance than the n.sup.+ type semiconductor layer is formed as if surrounded by a p.sup.+ type semiconductor region. The dielectric layer consists of a relatively thick first region and a relatively thin second region. The n.sup.+ type semiconductor region, which is located above the first region, occupies a narrower area than the first region. Thus, by forming the dielectric layer thick immediately under the first semiconductor layer and controlling the thickness of the dielectric layer at other potions, the breakdown voltage of the semiconductor device is improved without curbing RESURF effect.

Abstract: An object of the present invention is to provide a semiconductor device which is designed so as to increase a maximum controllable current and decrease hold current without degrading its characteristic and to provide a method of manufacturing such a semiconductor device. A transistor formation region 3 and a P diffusion region 15 are selectively formed through an insulating film 4 between gate electrodes 5 on an N.sup.- epitaxial layer 2. In a transistor formation region 3, an N.sup.+ diffusion region 12 is formed on a P diffusion region 11, a P diffusion region 13 is formed on the N.sup.+ diffusion region 12, and an N.sup.+ diffusion region 14 is selectively formed on a surface of the P diffusion region 13. Then, a cathode electrode 7 is formed on the P diffusion region 13, N.sup.+ diffusion region 14 and P diffusion region 15, and an anode electrode 8 is formed on a second major surface of the P.sup.+ substrate 1.

Abstract: A general object of the present invention is to make a maximum controllable current large without exerting adverse effect on other characteristics. In a surface of an n.sup.- layer 2 formed on a p.sup.+ substrate 1, p diffusion regions 3a, 3b and 3c are formed separated by n.sup.+ diffusion regions 4a, 4b and an oxidation film 9. Above the p diffusion regions 3a and 3b, gate electrodes 5a and 5b are formed insulated from the surrounding by an oxidation film 6. An Al--Si electrode 7 is in contact with the p diffusion region 3a and the n.sup.+ diffusion region 4a while a metal electrode 8 is in contact with the p.sup.+ substrate 1. By virtue of interposition of the oxidation film 9, a thyristor consisting of the n.sup.+ diffusion region 4a , p diffusion region 3a, n.sup.- layer 2 and p.sup.+ substrate 1 is prevented from being actuated.

Abstract: The present invention relates to a semiconductor device which is fabricated in simple process steps and which prevents deterioration in a breakdown voltage. Two diffusion regions are formed in space in a surface of an n.sup.- type layer. The diffusion regions are separated from each other by an insulation layer, but each in contact with a conductive film. Another conductive film is disposed on the insulation layer. The three conductive films are insulated from each other by the insulation layer and still another overlying insulation layer. Still other conductive films are formed on the upper insulation layer, and are coupled to the three conductive films. A wiring conductive film is also formed on the upper insulation layer. The wiring conductive film has a relatively small capacitance with the three conductive films. Due to the device structure, influence of the wiring conductive film over the surface of the semiconductor device is blocked by the conductive films.

Abstract: In a high breakdown voltage type semiconductor device, width W2 of channel region 20 at a corner portion is made wider than width W1 of channel region 20 at a linear portion in a planar pattern of a gate electrode 9. Consequently, the device has high breakdown voltage when it is "OFF" and has low resistance when it is "ON".

Abstract: A general object of the present invention is to make a maximum controllable current large without exerting adverse effect on other characteristics. In a surface of an n.sup.- layer 2 formed on a p.sup.+ substrate 1, p diffusion regions 3a, 3b and 3c are formed separated by n.sup.+ diffusion regions 4a, 4b and an oxidation film 9. Above the p diffusion regions 3b and 3c, gate electrodes 5a and 5b are formed insulated from the surrounding by an oxidation film 6. An Al-Si electrode 7 is in contact with the p diffusion region 3a and the n.sup.+ diffusion region 4a while a metal electrode 8 is in contact with the p.sup.+ substrate 1. By virtue of interposition of the oxidation film 9, a thyristor consisting of the n.sup.+ diffusion region 4a, p diffusion region 3a, n.sup.- layer 2 and p.sup.+ substrate 1 is prevented from being actuated.

Abstract: There is disclosed an IGBT which includes an n.sup.+ layer (2A), an n.sup.- layer (2B), a p well region (3), an n.sup.+ diffusion region (4), a gate oxide film (5), a gate electrode (6) and an emitter electrode (8) around the upper major surface of a p.sup.+ substrate (1), similarly to conventional IGBTs. In the lower major surface of the p.sup.+ substrate (1) is formed an n.sup.+ diffusion region (10) which adapted not to reach the n.sup.+ layer (2A). The n.sup.+ diffusion region (10) and p.sup.+ substrate (1) are connected to a collector electrode (9). When there is a small potential difference between the emitter and collector electrodes, holes are injected from the p.sup.+ substrate into the n.sup.- layer to provide a low ON-resistance. When the potential difference is large, a depletion layer extending from the n.sup.+ diffusion region is brought into a reach-through state to limit an increase in the amount of injected holes.

Abstract: Between electrodes (9) and (10) are formed a p.sup.+ substrate (2), an n.sup.- epitaxial layer (1) having a protruding portion (3), an n.sup.+ diffusion region (4) and p.sup.+ diffusion regions (13). Control electrodes (6) are formed on insulating films (5) on opposite sides of the protruding portion (3) and n.sup.+ diffusion region (4). The potential at the control electrodes (6) is increased or decreased with the potential at an electrode (10) increased relative to an electrode (9) to generate potential barrier or conductivity modulation in the n.sup.- epitaxial layer (1), whereby a semiconductor device turns off or on. Introduced holes are drawn through the p.sup.+ diffusion regions (13) when the semiconductor device turns off, to provide a small resistance and a short distance when the holes are drawn without changes in the area of the n.sup.+ diffusion region (4). This permits the semiconductor device to have small switching loss and high switching speed with a low ON-voltage.

Abstract: A semiconductor device includes an N.sup.- type semiconductor layer (2). The N.sup.- type semiconductor layer (2) includes a triangular pole trench (10), an apex portion thereof contains a gate electrode (5). The trench (10) penetrates the semiconductor layer (2) and a P type well region (3) and projects into an N.sup.+ type source region (4). A source electrode (7) is disposed so as to be insulated from the semiconductor layer (2) by an oxide film (9) and in contact with the well region (3) and the source region (4). A drain electrode (8) is connected to the semiconductor layer (2) through an N.sup.+ type semiconductor substrate (1). With higher potential at the gate electrode (5) than at the source electrode (7), the well region (3) is partially inverted into N type near the trench (10). Thus, the semiconductor device is turned on due to a channel created associated to the conductivity type inversion. Most of current flow allowed in the semiconductor layer (2) by the channel flows near the trench (10).

Abstract: There is provided p diffusion regions (18a, 18b) in the surface of an end portion of the n island (7) formed on the p.sup.- substrate (12). The insulation film (14) is formed on the n island (7) to form therein conductive plates (16a-16e). The p diffusion regions (18a, 18b) and, the conductive plates (16a-16e) are alternately arranged and so aligned that adjacent pairs of end portions thereof overlap with each other. Capacitances of capacitive coupling of the conductive plates (16a-16e) and the p diffusion regions (18a, 18b) are optimized so that potentials of the conductive plates (16a-16e) and the p diffusion regions (18a, 18b) can substantially linearly change from a low level to a high level. Thus, the concentration of electric field can be prevented.

Abstract: A thyristor structure comprises a p.sup.+ -type substrate (21), an n-type base layer (22), a first p-type diffusion region (23) and an n.sup.+ -type diffusion region (25). A MOS structure comprises the base layer (22), first and second p-type diffusion regions (23, 24) and the n.sup.+ -type diffusion region (25). A positive voltage is applied to a gate electrode (27) to form a channel in a portion of the first diffusion region (23) just under the gate electrode (27), so that a cathode electrode (28) supplies carriers to the base layer (22) through the n.sup.+ -type diffusion region (25) and the channel, to turn on the thyristor. A negative voltage is applied to the gate electrode (27) to form a channel in a portion of the base layer (22) just under the gate electrode (27), so that the first p-type diffusion region (23) and the n.sup.+ -type diffusion region (25) are shorted through the channel, the second p-type diffusion region (24) and the cathode electrode (28), to turn off the thyristor.

Abstract: Between electrodes (9) and (10) are formed a p.sup.+ substrate (2), an n.sup.- epitaxial layer (1) having a protruding portion (3), an n.sup.+ diffusion region (4) and p.sup.+ diffusion regions (13). Control electrodes (6) are formed on insulating films (5) on opposite sides of the protruding portion (3) and n.sup.+ diffusion region (4). The potential at the control electrodes (6) is increased or decreased with the potential at an electrode (10) increased relative to an electrode (9) to generate potential barrier or conductivity modulation in the n.sup.- epitaxial layer (1), whereby a semiconductor device turns off or on. Introduced holes are drawn through the p.sup.+ diffusion regions (13) when the semiconductor device turns off, to provide a small resistance and a short distance when the holes are drawn without changes in the area of the n.sup.+ diffusion region (4). This permits the semiconductor device to have small switching loss and high switching speed with a low ON-voltage.

Abstract: A semiconductor device includes an N.sup.- type semiconductor layer (2). The N.sup.- type semiconductor layer (2) includes a triangular pole trench (10), an apex portion thereof contains a gate electrode (5). The trench (10) penetrates the semiconductor layer (2) and a P type well region (3) and projects into an N.sup.+ type source region (4). A source electrode (7) is disposed so as to be insulated from the semiconductor layer (2) by an oxide film (9) and in contact with the well region (3) and the source region (4). A drain electrode (8) is connected to the semiconductor layer (2) through an N.sup.+ type semiconductor substrate (1). With a higher potential at the gate electrode (5) than at the source electrode (7), the well region (3) is partially inverted into N type near the trench (10). Thus, the semiconductor device is turned on due to a channel created associated to the conductivity type inversion. Most of current flow allowed in the semiconductor layer (2) by the channel flows near the trench (10).

Abstract: There is disclosed an IGBT which includes an n.sup.+ layer (2A) , an n.sup.- layer (2B) , a p well region (3), an n.sup.+ diffusion region (4), a gate oxide film (5), a gate electrode (6) and an emitter electrode (8) around the upper major surface of a p.sup.+ substrate (1), similarly to conventional IGBTS. In the lower major surface of the p.sup.+ substrate (1) is formed an n.sup.+ diffusion region (10) which is adapted not to reach the n.sup.+ layer (2A) . The n.sup.+ diffusion region (10) and p.sup.+ substrate (1) are connected to a collector electrode (9) . When there is a small potential difference between the emitter and collector electrodes, holes are injected from the p.sup.+ substrate into the n.sup.- layer to provide a low ON-resistance. When the potential difference is large, a depletion layer extending from the n.sup.+ diffusion region is brought into a reach-through state to limit an increase in the amount of injected holes.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: Conductive plates (16a-16e), or floating semiconductor regions (17a-17d), or conductive plates (16a, 16c, 16e) and floating semiconductor regions (17a, 17d) are disposed in alignment so that a coupling capacitance between the conductive plates and/or the floating semiconductor regions which are adjacent to each other decrease as a distance from a first or second semiconductor region (12, 13) increases. Therefore, the respective potentials at the conductive plates or the floating semiconductor regions can be varied linearly (or at equal potential differences), and corresponding potential distribution can be achieved on the surface of a semiconductor substrate (11). As a result, electric field concentration on the surface of the semiconductor substrate (11) just under a high potential conductive layer (14) can be prevented effectively even by the use of an insulating layer (15) with a common thickness.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: There is provided p diffusion regions (18a, 18b) in the surface of an end portion of the n island (7) formed on the p.sup.- substrate (12). The insulation film (14) is formed on the n island (7) to form therein conductive plates (16a-16e). The p diffusion regions (18a, 18b) and the conductive plates (16a-16e) are alternately arranged and so aligned that adjacent pairs of end portions thereof overlap with each other. Capacitances of capacitive coupling of the conductive plates (16a-16e) and the p diffusion regions (18a, 18b) are optimized so that potentials of the conductive plates (16a-16e) and the p diffusion regions (18a, 18b) can substantially linearly change from a low level to a high level. Thus, the concentration of electric field can be prevented.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.31 epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: A thyristor of the present invention turns on by applying a specified voltage to a first control electrode and turns off by applying a specified voltage to a second control electrode. These first and second control electrodes are independent of each other, so that the turning-on and turning-off conditions can be determined independently. When a transistor having the second control electrode is turned on by applying the specified voltage to the second control electrode until just before the turning-on, a first main electrode and a first semiconductor region can be electrically connected, so that the back gate potential of the transistor having the first control electrode can be fixed at the potential of the first main electrode.