Patents by Inventor Tomohito Tsushima
Tomohito Tsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140177316Abstract: A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Inventors: Wataru Otsuka, Jun Sumino, Tomohito Tsushima, Makoto Kitagawa, Takafumi Kunihiro
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Publication number: 20140022833Abstract: A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.Type: ApplicationFiled: September 25, 2013Publication date: January 23, 2014Applicant: Sony CorporationInventors: Makoto Kitagawa, Tsunenori Shiimoto, Tomohito Tsushima
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Patent number: 8576608Abstract: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.Type: GrantFiled: December 5, 2011Date of Patent: November 5, 2013Assignee: Sony CorporationInventors: Tomohito Tsushima, Makoto Kitagawa, Tsunenori Shiimoto, Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata
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Patent number: 8570787Abstract: A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.Type: GrantFiled: February 15, 2012Date of Patent: October 29, 2013Assignee: Sony CorporationInventors: Makoto Kitagawa, Tsunenori Shiimoto, Tomohito Tsushima
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Patent number: 8569732Abstract: A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen.Type: GrantFiled: November 23, 2011Date of Patent: October 29, 2013Assignee: Sony CorporationInventors: Shuichiro Yasuda, Tomohito Tsushima, Satoshi Sasaki, Katsuhisa Aratani
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Patent number: 8446756Abstract: Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes 21 and 24 in a variable resistance element 2. Diffusion loss of a conductive path caused by self-heat generation (generation of Joule heat) of the variable resistance element 2 may be prevented, and thus data hold operation after write is stabilized. Also, the variable resistance element 2 may be prevented from being destructed when the write operation is sufficiently performed, and thus the data write operation is stabilized.Type: GrantFiled: August 12, 2008Date of Patent: May 21, 2013Assignee: Sony CorporationInventors: Tsunenori Shiimoto, Nobumichi Okazaki, Tomohito Tsushima
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Patent number: 8416602Abstract: A nonvolatile semiconductor memory device includes: a memory element in which a rate of charge discharge between two electrodes of the memory element differs according to a logical value of stored information; cell wiring connected to one electrode of the memory element; a sense amplifier having a sense node connected to the cell wiring, the sense amplifier reading the logical value of the information by comparing a potential of the sense node with a reference potential; and a readout control circuit capable of switching between a dynamic sense operation performing readout by precharging the cell wiring and discharging or charging the cell wiring via the memory element and a static sense operation performing readout in a state of a current load being connected to the sense node.Type: GrantFiled: January 20, 2011Date of Patent: April 9, 2013Assignee: Sony CorporationInventors: Makoto Kitagawa, Tsunenori Shiimoto, Tomohito Tsushima
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Patent number: 8369128Abstract: A storage device capable of decreasing the number of voltages necessitating control and decreasing peripheral circuit size is provided. A first pulse voltage (VBLR) is supplied from a first power source through a bit line BLR to an electrode of a variable resistive element. A second pulse voltage (VWL) for selecting a cell is supplied from a second power source through a word line WL to a control terminal of a transistor. A third pulse voltage (VBLT) is supplied from a third power source though a bit line BLT to a second input/output terminal of the transistor. At the time of rewriting information, the voltage value (VBLT) of the third power source is adjusted by an adjustment circuit. Thereby, a cell voltage and a cell current are changed (decreased or increased).Type: GrantFiled: December 11, 2008Date of Patent: February 5, 2013Assignee: Sony CorporationInventors: Tsunenori Shiimoto, Tomohito Tsushima, Shuichiro Yasuda
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Patent number: 8363447Abstract: A storage device capable of reducing a number of cycles necessary for a verify at a time of multi-bit recording is provided. An initial value of a potential difference VGS between a gate and a source of a switching transistor at the time of the verify is set to a value varied based on a resistance value level of multi-bit information. In the case of recording 2 bits when “01” is the information, an initial value VGS01 is set to be smaller than VGS=1.7 V corresponding to the target resistance value level “01”, and when “00” is the information, a value is set to be lower than VGS=2.2 V corresponding to the target resistance value level “00” and higher than the above-described VGS01. This can reduce the number of cycles necessary for the verify process.Type: GrantFiled: December 11, 2008Date of Patent: January 29, 2013Assignee: Sony CorporationInventors: Tomohito Tsushima, Tsunenori Shiimoto, Shuichiro Yasuda
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Patent number: 8350248Abstract: A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen.Type: GrantFiled: January 7, 2009Date of Patent: January 8, 2013Assignee: Sony CorporationInventors: Shuichiro Yasuda, Tomohito Tsushima, Satoshi Sasaki, Katsuhisa Aratani
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Publication number: 20120218809Abstract: A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.Type: ApplicationFiled: February 15, 2012Publication date: August 30, 2012Applicant: Sony CorporationInventors: Makoto Kitagawa, Tsunenori Shiimoto, Tomohito Tsushima
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Publication number: 20120212994Abstract: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.Type: ApplicationFiled: December 5, 2011Publication date: August 23, 2012Applicant: Sony CorporationInventors: Tomohito Tsushima, Makoto Kitagawa, Tsunenori Shiimoto, Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata
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Patent number: 8213214Abstract: A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ?VWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ?VWL is a value variable for every resistance value level of multiple value information. That is, ?VWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ?VWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ?VWL is large.Type: GrantFiled: December 11, 2008Date of Patent: July 3, 2012Assignee: Sony CorporationInventors: Tomohito Tsushima, Tsunenori Shiimoto, Shuichiro Yasuda
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Publication number: 20120069631Abstract: A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen.Type: ApplicationFiled: November 23, 2011Publication date: March 22, 2012Applicant: Sony CorporationInventors: Shuichiro Yasuda, Tomohito Tsushima, Satoshi Sasaki, Katsuhisa Aratani
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Nonvolatile semiconductor memory device and method for performing verify write operation on the same
Patent number: 8102716Abstract: Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit, writing data collectively to the predetermined number of memory cells, and verifying the written data, the driver circuit further performing the verify write operation repeatedly until all memory cells within the write cell unit are found to have passed the verification.Type: GrantFiled: January 4, 2010Date of Patent: January 24, 2012Assignee: Sony CorporationInventors: Tsunenori Shiimoto, Makoto Kitagawa, Tomohito Tsushima -
Publication number: 20110199812Abstract: A nonvolatile semiconductor memory device includes: a memory element in which a rate of charge discharge between two electrodes of the memory element differs according to a logical value of stored information; cell wiring connected to one electrode of the memory element; a sense amplifier having a sense node connected to the cell wiring, the sense amplifier reading the logical value of the information by comparing a potential of the sense node with a reference potential; and a readout control circuit capable of switching between a dynamic sense operation performing readout by precharging the cell wiring and discharging or charging the cell wiring via the memory element and a static sense operation performing readout in a state of a current load being connected to the sense node.Type: ApplicationFiled: January 20, 2011Publication date: August 18, 2011Applicant: Sony CorporationInventors: Makoto Kitagawa, Tsunenori Shiimoto, Tomohito Tsushima
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Publication number: 20110149635Abstract: A storage device capable of decreasing the number of voltages necessitating control and decreasing peripheral circuit size is provided. A first pulse voltage (VBLR) is supplied from a first power source through a bit line BLR to an electrode of a variable resistive element. A second pulse voltage (VWL) for selecting a cell is supplied from a second power source through a word line WL to a control terminal of a transistor. A third pulse voltage (VBLT) is supplied from a third power source though a bit line BLT to a second input/output terminal of the transistor. At the time of rewriting information, the voltage value (VBLT) of the third power source is adjusted by an adjustment circuit. Thereby, a cell voltage and a cell current are changed (decreased or increased).Type: ApplicationFiled: December 11, 2008Publication date: June 23, 2011Applicant: SONY CORPORATIONInventors: Tsunenori Shiimoto, Tomohito Tsushima, Shuichiro Yasuda
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Publication number: 20110073825Abstract: A memory device 10 having an arrangement in which a memory thin film is sandwiched between first and second electrodes, the memory thin film contains at least rare earth elements, the memory thin film 4 or a layer in contact with the memory thin film contains any one of elements selected from Cu, Ag, Zn and the memory thin film or the layer in contact with the memory thin film contains any one of elements selected from Te, S, Se.Type: ApplicationFiled: December 6, 2010Publication date: March 31, 2011Applicant: SONY CORPORATIONInventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
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Publication number: 20110026298Abstract: Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes 21 and 24 in a variable resistance element 2. Diffusion loss of a conductive path caused by self-heat generation (generation of Joule heat) of the variable resistance element 2 may be prevented, and thus data hold operation after write is stabilized. Also, the variable resistance element 2 may be prevented from being destructed when the write operation is sufficiently performed, and thus the data write operation is stabilized.Type: ApplicationFiled: August 12, 2008Publication date: February 3, 2011Applicant: SONY CORPORATIONInventors: Tsunenori Shiimoto, Nobumichi Okazaki, Tomohito Tsushima
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Publication number: 20100259968Abstract: A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ?VWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ?VWL is a value variable for every resistance value level of multiple value information. That is, ?VWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ?VWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ?VWL is large.Type: ApplicationFiled: December 11, 2008Publication date: October 14, 2010Applicant: SONY CORPORATIONInventors: Tomohito Tsushima, Tsunenori Shiimoto, Shuichiro Yasuda