Patents by Inventor Tomohito Tsushima

Tomohito Tsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7126152
    Abstract: A storage device includes a first electrode, a second electrode facing the first electrode, an inter-electrode material layer provided between the first electrode and the second electrode, and a voltage application unit applying a predetermined voltage to the first and the second electrodes. Furthermore, an oxidation-reduction active material changeable into an electrode reaction inhibition layer by applying voltages to the first and the second electrodes is contained in a region that is covered by an electric field, the electric field being generated when the voltage is applied, and the electrode reaction inhibition layer is either formed along an interface region between the second electrode and the inter-electrode material layer, or changes an area thereof, or disappears depending on an application condition of the voltage to the first and the second.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: October 24, 2006
    Assignee: Sony Corporation
    Inventors: Minoru Ishida, Katsuhisa Aratani, Akira Kouchiyama, Tomohito Tsushima
  • Patent number: 7092278
    Abstract: Data reading can be easily and precisely performed by setting specific conditions in writing into a selected memory cell. A memory cell has a structure, in which an interelectrode material layer is sandwiched between a first electrode and a second electrode. Data is stored by a change in a resistance value between the first electrode and the second electrode. The resistance value when a memory element is in a high resistance state is expressed as R_mem_high; the resistance value when the memory element is in a low resistance state is expressed as R_mem_low1; the resistance value of a load circuit is expressed as R_load; the reading voltage is expressed as Vread by setting the voltage of a second power supply line to the reference voltage; and the threshold voltage is expressed as Vth_critical. In writing data into the memory cell, the low resistance state is created so that these parameters satisfy specific relations.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: August 15, 2006
    Assignee: Sony Corporation
    Inventors: Minoru Ishida, Katsuhisa Aratani, Akira Kouchiyama, Tomohito Tsushima
  • Publication number: 20060109316
    Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
    Type: Application
    Filed: October 4, 2005
    Publication date: May 25, 2006
    Inventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
  • Publication number: 20060104106
    Abstract: A memory element is provided in which recording and erasure of information can be performed easily and stably. A memory element 10 includes a memory layer 4 positioned between a first electrode 2 and a second electrode 6, in which an element selected from Cu, Ag, and Zn is contained in the memory layer 4 or in a layer 3 in contact with the memory layer 4, a resistance of the memory element 10 is changed by a voltage applied to the memory element 10 to perform recording of information, and in an erasing process of changing from a recorded state of low resistance value of the memory element 10 to an erased state of high resistance value of the memory element 10, a fluctuation, which is caused by an increase of the voltage applied to the memory element 10, of the resistance value of the memory element 10 at the end of the erasing process is within ten times at a maximum.
    Type: Application
    Filed: November 15, 2005
    Publication date: May 18, 2006
    Applicant: Sony Corporation
    Inventors: Katsuhisa Aratani, Tomohito Tsushima, Akira Kouchiyama, Tetsuya Mizuguchi
  • Publication number: 20060092691
    Abstract: A memory element having a configuration in which contents of recorded data can be judged easily and power consumption can be reduced, and a method of driving the same are provided. A memory element 10 of the present invention includes variable resistance elements 11 and 12 whose resistance state changes reversibly between a high resistance state and a low resistance state by applying a voltage of a different polarity between an electrode 1 of one side and an electrode 2 of the other side; the electrode 1 of one side in each element of the two variable resistance elements 11 and 12 is made a common electrode; and the electrode 2 of the other side in each element of the two variable resistance elements 11 and 12 is made independent and is provided respectively with the terminal X and terminal Y, to form a memory cell having two terminals in total.
    Type: Application
    Filed: November 2, 2005
    Publication date: May 4, 2006
    Applicant: Sony Corporation
    Inventors: Tsunenori Shiimoto, Katsuhisa Aratani, Masaaki Hara, Tomohito Tsushima
  • Publication number: 20060092685
    Abstract: The present invention provides a storage apparatus including a variable resistance element having a recording layer between two electrodes. In the variable resistance element, a resistance value of the recording layer is reversibly changed to one of a value in a high-resistance state and a value in a low-resistance state by applying potentials of different polarities to the two electrodes. An absolute value of a threshold value of an applied signal at a time of change from the high-resistance state to the low-resistance state and an absolute value of a threshold value of an applied signal at a time of change from the low-resistance state to the high-resistance state differ from each other. A reading signal for detecting the resistance value of the recording layer in the variable resistance element is applied with a polarity of one of the threshold values of the applied signals which one has a higher absolute value and with a value lower than the absolute value.
    Type: Application
    Filed: October 5, 2005
    Publication date: May 4, 2006
    Inventors: Wataru Ootsuka, Tomohito Tsushima, Hidenari Hachino
  • Publication number: 20060067114
    Abstract: A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 30, 2006
    Inventors: Hidenari Hachino, Nobumichi Okazaki, Wataru Otsuka, Tomohito Tsushima, Tsutomu Sagara, Chieko Nakashima, Hironobu Mori, Hajime Nagao
  • Patent number: 7016234
    Abstract: A storage device is provided. The storage device includes a number of storage cells arranged and each having a storage element and an active element including a MOS transistor that controls access to the storage element, and in which applying a voltage to the storage element the resistance value of the storage element changes and information is recorded wherein the resistance value of a storage element after information has been written is prevented from becoming lower than necessary and in which information writing can be easily performed.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: March 21, 2006
    Assignee: Sony Corporation
    Inventors: Minoru Ishida, Katsuhisa Aratani, Akira Kouchiyama, Tomohito Tsushima
  • Publication number: 20050226036
    Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.
    Type: Application
    Filed: November 17, 2004
    Publication date: October 13, 2005
    Inventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
  • Publication number: 20050195634
    Abstract: Data reading can be easily and precisely performed by setting specific conditions in writing into a selected memory cell. A memory cell has a structure, in which an interelectrode material layer is sandwiched between a first electrode and a second electrode. Data is stored by a change in a resistance value between the first electrode and the second electrode. The resistance value when a memory element is in a high resistance state is expressed as R_mem_high; the resistance value when the memory element is in a low resistance state is expressed as R_mem_low1; the resistance value of a load circuit is expressed as R_load; the reading voltage is expressed as Vread by setting the voltage of a second power supply line to the reference voltage; and the threshold voltage is expressed as Vth_critical. In writing data into the memory cell, the low resistance state is created so that these parameters satisfy specific relations.
    Type: Application
    Filed: March 3, 2005
    Publication date: September 8, 2005
    Inventors: Minoru Ishida, Katsuhisa Aratani, Akira Kouchiyama, Tomohito Tsushima
  • Publication number: 20050174854
    Abstract: A memory device is obtained in which stable recording of information can be performed and a period of time required for the recording of information can be shortened.
    Type: Application
    Filed: January 25, 2005
    Publication date: August 11, 2005
    Applicant: Sony Corporation
    Inventors: Tomohito Tsushima, Katsuhisa Aratani, Akira Kouchiyama
  • Publication number: 20050174840
    Abstract: A memory device is provided in which recording of multi-valued data can be performed at a high speed and the recording of multi-valued data can be performed with a drive circuit having comparatively simple configuration.
    Type: Application
    Filed: January 18, 2005
    Publication date: August 11, 2005
    Applicant: Sony Corporation
    Inventors: Tomohito Tsushima, Katsuhisa Aratani, Akira Kouchiyama
  • Publication number: 20050121697
    Abstract: A storage device includes a first electrode, a second electrode facing the first electrode, an inter-electrode material layer provided between the first electrode and the second electrode, and a voltage application unit applying a predetermined voltage to the first and the second electrodes. Furthermore, an oxidation-reduction active material changeable into an electrode reaction inhibition layer by applying voltages to the first and the second electrodes is contained in a region that is covered by an electric field, the electric field being generated when the voltage is applied, and the electrode reaction inhibition layer is either formed along an interface region between the second electrode and the inter-electrode material layer, or changes an area thereof, or disappears depending on an application condition of the voltage to the first and the second.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 9, 2005
    Inventors: Minoru Ishida, Katsuhisa Aratani, Akira Kouchiyama, Tomohito Tsushima
  • Publication number: 20050035373
    Abstract: A storage device is provided. The storage device includes a number of storage cells arranged and each having a storage element and an active element including a MOS transistor that controls access to the storage element, and in which applying a voltage to the storage element the resistance value of the storage element changes and information is recorded wherein the resistance value of a storage element after information has been written is prevented from becoming lower than necessary and in which information writing can be easily performed.
    Type: Application
    Filed: July 2, 2004
    Publication date: February 17, 2005
    Inventors: Minoru Ishida, Katsuhisa Aratani, Akira Kouchiyama, Tomohito Tsushima