Patents by Inventor Tomomasa Ueda

Tomomasa Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12089395
    Abstract: A semiconductor device of an embodiment is provided with: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; a first conductive layer provided at least one of positions between the first region and the first electrode or between the second region and the second electrode and containing a first metal element and at least one element of oxygen (O) or nitrogen (N); and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer and containing oxygen (O) and at least one element selected from indium (In), zinc (Zn), tin (Sn), or cadmium (Cd). The second conductive layer is thicker than the first conductive layer.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: September 10, 2024
    Assignee: Kioxia Corporation
    Inventors: Yuta Sato, Tomomasa Ueda, Nobuyoshi Saito, Keiji Ikeda
  • Patent number: 11942545
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Yuta Sato, Tomomasa Ueda, Nobuyoshi Saito, Keiji Ikeda
  • Patent number: 11769810
    Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Junji Kataoka, Tomomasa Ueda, Shushu Zheng, Nobuyoshi Saito, Keiji Ikeda
  • Publication number: 20220406934
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
  • Publication number: 20220302120
    Abstract: A semiconductor device of an embodiment is provided with: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; a first conductive layer provided at least one of positions between the first region and the first electrode or between the second region and the second electrode and containing a first metal element and at least one element of oxygen (O) or nitrogen (N); and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer and containing oxygen (O) and at least one element selected from indium (In), zinc (Zn), tin (Sn), or cadmium (Cd). The second conductive layer is thicker than the first conductive layer.
    Type: Application
    Filed: September 9, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
  • Patent number: 11430886
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yuta Sato, Tomomasa Ueda, Nobuyoshi Saito, Keiji Ikeda
  • Patent number: 11374130
    Abstract: A semiconductor device of an embodiment includes: a first oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a second oxide semiconductor layer provided in at least one of a position between the first region and the first electrode and a position between the second region and the second electrode and containing indium (In), aluminum (Al), and zinc (Zn), an atomic ratio of aluminum to a sum of indium, aluminum, and zinc being 8% or more and 23% or less, and an atomic ratio of indium to the sum of indium, aluminum, and zinc being 45% or less.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 28, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shigeki Hattori, Tomomasa Ueda, Keiji Ikeda
  • Publication number: 20220085212
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Application
    Filed: March 11, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
  • Publication number: 20220085182
    Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.
    Type: Application
    Filed: March 11, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Junji KATAOKA, Tomomasa UEDA, Shushu ZHENG, Nobuyoshi SAITO, Keiji IKEDA
  • Publication number: 20210249540
    Abstract: A semiconductor device of an embodiment includes: a first oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a second oxide semiconductor layer provided in at least one of a position between the first region and the first electrode and a position between the second region and the second electrode and containing indium (In), aluminum (Al), and zinc (Zn), an atomic ratio of aluminum to a sum of indium, aluminum, and zinc being 8% or more and 23% or less, and an atomic ratio of indium to the sum of indium, aluminum, and zinc being 45% or less.
    Type: Application
    Filed: August 24, 2020
    Publication date: August 12, 2021
    Applicant: Kioxia Corporation
    Inventors: Shigeki HATTORI, Tomomasa UEDA, Keiji IKEDA
  • Patent number: 11024719
    Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 1, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoaki Sawabe, Nobuyoshi Saito, Junji Kataoka, Tomomasa Ueda, Keiji Ikeda
  • Patent number: 10950735
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junji Kataoka, Tomomasa Ueda, Tomoaki Sawabe, Keiji Ikeda, Nobuyoshi Saito
  • Publication number: 20200381557
    Abstract: According to an embodiment, a semiconductor device includes an oxide semiconductor layer including indium (In), aluminum (Al), and zinc (Zn), the oxide semiconductor layer having an atomic ratio of the aluminum to a sum of indium, aluminum, and zinc of equal to or more than 8% and equal to or less than 23%, a gate electrode, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode.
    Type: Application
    Filed: March 4, 2020
    Publication date: December 3, 2020
    Applicant: Kioxia Corporation
    Inventors: Shigeki HATTORI, Tomomasa UEDA, Keiji IKEDA
  • Patent number: 10790396
    Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoaki Sawabe, Tomomasa Ueda, Keiji Ikeda, Tsutomu Tezuka, Nobuyoshi Saito
  • Publication number: 20200303554
    Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoaki SAWABE, Nobuyoshi SAITO, Junji KATAOKA, Tomomasa UEDA, Keiji IKEDA
  • Patent number: 10714629
    Abstract: According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Kentaro Miura, Keiji Ikeda, Tsutomu Tezuka
  • Patent number: 10553601
    Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura, Tomoaki Sawabe
  • Publication number: 20200013892
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.
    Type: Application
    Filed: March 12, 2019
    Publication date: January 9, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Junji KATAOKA, Tomomasa UEDA, Tomoaki SAWABE, Keiji IKEDA, Nobuyoshi SAITO
  • Patent number: 10497712
    Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura, Tomoaki Sawabe
  • Publication number: 20190296155
    Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.
    Type: Application
    Filed: August 14, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoaki SAWABE, Tomomasa UEDA, Keiji IKEDA, Tsutomu TEZUKA, Nobuyoshi SAITO