Patents by Inventor Tomomasa Ueda

Tomomasa Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120132909
    Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; a source electrode and a drain electrode provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source electrode and the drain electrode above the gate electrode.
    Type: Application
    Filed: February 3, 2012
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Shintaro Nakano, Shuichi Uchikoga
  • Patent number: 8173447
    Abstract: A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned magnetization direction; a first tunnel barrier layer provided between the magnetization free layer and the magnetization pinned layer; a second tunnel barrier layer provided on the second plane of the magnetization free layer; and a non-magnetic layer provided on a plane on the opposite side of the second tunnel barrier layer from the magnetization free layer. The magnetization direction of the magnetization free layer is variable by applying current between the magnetization pinned layer and the non-magnetic layer, and a resistance ratio between the first tunnel barrier layer and the second tunnel barrier layer is in a range of 1:0.25 to 1:4.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Hisanori Aikawa, Masatoshi Yoshikawa, Naoharu Shimomura, Masahiko Nakayama, Sumio Ikegawa, Keiji Hosotani, Makoto Nagamine
  • Publication number: 20120075260
    Abstract: According to one embodiment, an active-matrix organic EL display device includes a display region and a peripheral region. The display region includes a plurality of pixels disposed in a matrix configuration. The peripheral region includes a drive circuit. The pixel includes a bottom gate-type first transistor, a cathode electrode, an anode electrode, and an organic EL layer provided between the cathode electrode and the anode electrode. The drive circuit includes a bottom gate-type second transistor and a back gate electrode provided on the second transistor. A gate potential of the first transistor is lower than a potential of the cathode electrode when the pixel displays a minimum luminance.
    Type: Application
    Filed: March 18, 2011
    Publication date: March 29, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi SAITO, Yujiro Hara, Tomomasa Ueda, Shintaro Nakano, Kentaro Miura
  • Publication number: 20120058601
    Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; source and drain electrodes provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source and drain electrodes above the gate electrode.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 8, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Shintaro Nakano, Shuichi Uchikoga
  • Publication number: 20110254114
    Abstract: A magnetoresistive effect element includes a first ferromagnetic layer formed above a substrate, a second ferromagnetic layer formed above the first ferromagnetic layer, an insulating layer interposed between the first ferromagnetic layer and the second ferromagnetic layer and formed of a metal oxide, and a first nonmagnetic metal layer interposed between the insulating layer and the second ferromagnetic layer and in contact with a surface of the insulating layer on the side of the second ferromagnetic layer, the first nonmagnetic metal layer containing the same metal element as the metal oxide.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Inventors: Makoto Nagamine, Keiji Hosotani, Hisanori Aikawa, Tomomasa Ueda, Sumio Ikegawa
  • Publication number: 20110164025
    Abstract: [Problem] By improving the accuracy of compensation for a threshold voltage shift of a driving transistor that controls a current supplied to a current-driven type self light-emitting element, excellent display performance is maintained over an extended period of time. [Solving Means] A pixel circuit includes a driving transistor Dr connected at its drain to a light-emitting element 11 and connected at its source to a power supply line NL; a capacitor Ck connected at its one end to a gate of the driving transistor Dr; a threshold voltage detection transistor Det connected between the drain of the driving transistor Dr and an other end of the capacitor Ck; and a reset transistor Rst connected between the source and gate of the driving transistor Dr.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 7, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi SAITO, Tomomasa Ueda, Yujiro Hara
  • Patent number: 7894246
    Abstract: A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned magnetization direction; a first tunnel barrier layer provided between the magnetization free layer and the magnetization pinned layer; a second tunnel barrier layer provided on the second plane of the magnetization free layer; and a non-magnetic layer provided on a plane on the opposite side of the second tunnel barrier layer from the magnetization free layer. The magnetization direction of the magnetization free layer is variable by applying current between the magnetization pinned layer and the non-magnetic layer, and a resistance ratio between the first tunnel barrier layer and the second tunnel barrier layer is in a range of 1:0.25 to 1:4.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: February 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Hisanori Aikawa, Masatoshi Yoshikawa, Naoharu Shimomura, Masahiko Nakayama, Sumio Ikegawa, Keiji Hosotani, Makoto Nagamine
  • Publication number: 20100315864
    Abstract: A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned magnetization direction; a first tunnel barrier layer provided between the magnetization free layer and the magnetization pinned layer; a second tunnel barrier layer provided on the second plane of the magnetization free layer; and a non-magnetic layer provided on a plane on the opposite side of the second tunnel barrier layer from the magnetization free layer. The magnetization direction of the magnetization free layer is variable by applying current between the magnetization pinned layer and the non-magnetic layer, and a resistance ratio between the first tunnel barrier layer and the second tunnel barrier layer is in a range of 1:0.25 to 1:4.
    Type: Application
    Filed: August 5, 2010
    Publication date: December 16, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomomasa UEDA, Hisanori Aikawa, Masatoshi Yoshikawa, Naoharu Shimomura, Masahiko Nakayama, Sumio Ikegawa, Keiji Hosotani, Makoto Nagamine
  • Patent number: 7848136
    Abstract: It is possible to reduce writing current without causing fluctuation of the writing characteristic. A magnetic memory includes: a magnetoresistance effect element having a magnetization pinned layer whose magnetization direction is pinned, a storage layer whose magnetization direction is changeable, and a non-magnetic layer provided between the magnetization pinned layer and the storage layer; and a first wiring layer which is electrically connected to the magnetoresistance effect element and extends in a direction substantially perpendicular to a direction of an easy magnetization axis of the storage layer, an end face of the magnetoresistance effect element substantially perpendicular to the direction of the easy magnetization axis of the storage layer and an end face of the first wiring layer substantially perpendicular to the direction of the easy magnetization axis being positioned on the same plane.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: December 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao, Hiroaki Yoda
  • Publication number: 20100127266
    Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; a source electrode and a drain electrode provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source electrode and the drain electrode above the gate electrode.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 27, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi SAITO, Tomomasa Ueda, Shintaro Nakano, Shuichi Uchikoga
  • Publication number: 20090251496
    Abstract: This disclosure concerns a display device including: scanning lines; data lines; a drive transistor controlling a current through a light emitting element; a bias transistor connected between a gate of the drive transistor and a first signal line transmitting a negative bias lower than a potential of the second power supply; a Vt detection transistor setting a threshold voltage of the drive transistor; a capacitor applying a potential difference between gate-source of the drive transistor; a scanning transistor setting a potential of the data line to the second electrode; a scanning line driver; and a data line driver transmitting potential data to the pixel columns, wherein before setting the threshold voltage to the first electrode, the bias transistor connects the first signal line to the gate of the drive transistor and applies the negative bias to the gate of the drive transistor.
    Type: Application
    Filed: March 13, 2009
    Publication date: October 8, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi SAITO, Tomomasa Ueda, Yujiro Hara
  • Publication number: 20090244045
    Abstract: This disclosure concerns a display device including an n-type drive transistor controlling a current flowing the light emitting element; a bias transistor; a Vt detection transistor; a capacitor; a scanning transistor, wherein before setting the first electrode of the capacitor to have the threshold voltage of the drive transistor, the bias transistor connects a first signal line to the gate of the drive transistor to apply the negative bias to the gate of the drive transistor, the scanning line driver sets the first electrode to have a higher level potential than the threshold voltage of the drive transistor, and the Vt detection transistor connects the gate to the drain of the drive transistor to set the first electrode to have the threshold voltage of the drive transistor.
    Type: Application
    Filed: March 11, 2009
    Publication date: October 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi SAITO, Tomomasa Ueda, Yujiro Hara
  • Patent number: 7564109
    Abstract: A magnetic memory device includes a first write wiring line including a wiring layer formed in a trench in an insulation layer, a barrier metal layer buried in the trench over the wiring layer. And the device includes a magneto-resistance effect element provided on the first write wiring line.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: July 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kajiyama, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Masatoshi Yoshikawa
  • Publication number: 20090079725
    Abstract: A display device includes: a drive circuit supplying a first signal voltage and a first reverse bias in a first frame time period, and supplying a second signal voltage and a second reverse bias in a second frame time period subsequent to the first frame time period; a first drive TFT receiving the first signal voltage to supply a first drive current based on the first signal voltage in the first frame time period, and receiving the second reverse bias in the second frame time period; a second drive TFT receiving the first reverse bias in the first frame time period, and receiving the second signal voltage to supply a second drive current based on the second signal voltage in the second frame time period; and a display element emitting light based on the first drive current in the first frame time period and emitting light based on the second drive current in the second frame time period.
    Type: Application
    Filed: September 15, 2008
    Publication date: March 26, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Yujiro Hara
  • Patent number: 7470963
    Abstract: There are provided a first reference layer, in which a direction of magnetization is fixed, and a storage layer including a main body, in which a length in an easy magnetization axis direction is longer than a length in a hard magnetization axis direction, and a projecting portion provided to a central portion of the main body in the hard magnetization axis direction, a direction of magnetization of the storage layer being changeable in accordance with an external magnetic field.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: December 30, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Kai, Shigeki Takahashi, Tomomasa Ueda, Tatsuya Kishi, Yoshiaki Saito
  • Publication number: 20080253039
    Abstract: A magnetoresistive effect element includes a first ferromagnetic layer formed above a substrate, a second ferromagnetic layer formed above the first ferromagnetic layer, an insulating layer interposed between the first ferromagnetic layer and the second ferromagnetic layer and formed of a metal oxide, and a first nonmagnetic metal layer interposed between the insulating layer and the second ferromagnetic layer and in contact with a surface of the insulating layer on the side of the second ferromagnetic layer, the first nonmagnetic metal layer containing the same metal element as the metal oxide.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 16, 2008
    Inventors: Makoto NAGAMINE, Keiji HOSOTANI, Hisanori AIKAWA, Tomomasa UEDA, Sumio IKEGAWA
  • Publication number: 20080204944
    Abstract: It is possible to reduce writing current without causing fluctuation of the writing characteristic. A magnetic memory includes: a magnetoresistance effect element having a magnetization pinned layer whose magnetization direction is pinned, a storage layer whose magnetization direction is changeable, and a non-magnetic layer provided between the magnetization pinned layer and the storage layer; and a first wiring layer which is electrically connected to the magnetoresistance effect element and extends in a direction substantially perpendicular to a direction of an easy magnetization axis of the storage layer, an end face of the magnetoresistance effect element substantially perpendicular to the direction of the easy magnetization axis of the storage layer and an end face of the first wiring layer substantially perpendicular to the direction of the easy magnetization axis being positioned on the same plane.
    Type: Application
    Filed: April 10, 2008
    Publication date: August 28, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao, Hiroaki Yoda
  • Publication number: 20080180859
    Abstract: A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned magnetization direction; a first tunnel barrier layer provided between the magnetization free layer and the magnetization pinned layer; a second tunnel barrier layer provided on the second plane of the magnetization free layer; and a non-magnetic layer provided on a plane on the opposite side of the second tunnel barrier layer from the magnetization free layer. The magnetization direction of the magnetization free layer is variable by applying current between the magnetization pinned layer and the non-magnetic layer, and a resistance ratio between the first tunnel barrier layer and the second tunnel barrier layer is in a range of 1:0.25 to 1:4.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 31, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomomasa UEDA, Hisanori AIKAWA, Masatoshi YOSHIKAWA, Naoharu SHIMOMURA, Masahiko NAKAYAMA, Sumio IKEGAWA, Keiji HOSOTANI, Makoto NAGAMINE
  • Patent number: 7333359
    Abstract: A write word line is disposed right under a MTJ element. The write word line extends in an X direction, and side and lower surfaces of the write word line are coated with a hard magnetic material and yoke material. The hard magnetic material is magnetized by a surplus current passed through the write word line, and a characteristic of the MTJ element is corrected by residual magnetization. A data selection line (read/write bit line) is disposed right on the MTJ element. The data selection line extends in a Y direction intersecting with the X direction, and a part of the surface of the data selection line is coated with the yoke material.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: February 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Yoshihisa Iwata, Yoshiaki Saito, Hiroaki Yoda, Tomomasa Ueda, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi
  • Patent number: 7291506
    Abstract: A method of manufacturing a magnetic memory device includes forming an insulation layer on a substrate, forming a lower electrode on the insulation layer, forming a magneto-resistive film on an upper surface of the lower electrode, the magneto-resistive film including an insulation barrier layer and a plurality of magnetic films stacked on both sides of the insulation barrier layer, stacking a mask layer on the magneto-resistive film, performing ion etching on the magneto-resistive film, using the mask layer as a mask, thereby forming a magneto-resistive element, forming an insulation film on upper surfaces of the mask, the magneto-resistive element and the lower electrode, and etching the insulation film with an ion beam such that a side surface of the magneto-resistive element is exposed.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: November 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Nakajima, Minoru Amano, Tomomasa Ueda, Shigeki Takahashi