Patents by Inventor Tomomasa Ueda

Tomomasa Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140284593
    Abstract: According to one embodiment, a semiconductor device includes a substrate having an upper surface, a foundation insulating layer provided on the upper surface, and a thin film transistor. The thin film transistor includes a first gate electrode, first, second and third insulating layers, a semiconductor layer, and first and second conductive layers. The first gate electrode is provided on a portion of the foundation insulating layer. The first insulating layer covers the first gate electrode and the foundation insulating layer. The second insulating layer is provided on the first insulating layer, and has first, second and third portions. The semiconductor layer contacts the second insulating layer on the third portion, and has fourth, fifth portions and sixth portions. The first conductive layer contacts the fourth portion. The second conductive layer contacts the fifth portion. The third insulating layer covers a portion of the semiconductor layer.
    Type: Application
    Filed: February 5, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Ikuo Fujiwara, Hajime Yamaguchi
  • Publication number: 20140246685
    Abstract: According to one embodiment, a method for manufacturing a display element is disclosed. The method can include forming a peeling layer, forming a resin layer, forming a barrier layer, forming an interconnect layer, forming a display layer, and removing. The peeling layer is formed on a major surface of a base body. The major surface has first, second, and third regions. The peeling layer includes first, second, and third peeling portions. The resin layer is formed on the peeling layer. The resin layer includes first and second resin portions. The barrier layer is formed on the first, second, and third peeling portions. The interconnect layer is formed on the barrier layer. The display layer is formed on the interconnect layer. The first peeling portion is removed from the first resin portion and the second peeling portion is removed from the second resin portion.
    Type: Application
    Filed: February 4, 2014
    Publication date: September 4, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro MIURA, Tatsunori SAKANO, Tomomasa UEDA, Nobuyoshi SAITO, Shintaro NAKANO, Yuya MAEDA, Hajime YAMAGUCHI
  • Publication number: 20140147948
    Abstract: According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Shintaro Nakano, Nobuyoshi Saito, Kentaro Miura, Yujiro Hara, Hajime Yamaguchi
  • Publication number: 20140138682
    Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; source and drain electrodes provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source and drain electrodes above the gate electrode.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi SAITO, Tomomasa UEDA, Shintaro NAKANO, Shuichi UCHIKOGA
  • Publication number: 20140084284
    Abstract: According to one embodiment, a display device includes a thin film transistor. The thin film transistor includes a gate insulating film, a semiconductor layer, a gate electrode, first and second channel protection films, first and second conductive layers, and a passivation film. The semiconductor layer is provided on a major surface of the gate insulating film. The semiconductor layer includes first to seventh portions. The gate insulating film is disposed between the semiconductor layer and the gate electrode. The first channel protection film covers the third portion. The second channel protection film covers the fifth and fourth portions, and an upper surface of the first channel protection film. The first conductive layer covers the sixth portion. The second conductive layer covers the seventh portion. The passivation film covers the first and second portions, the first and second conductive layers, and the second channel protection film.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Kentaro MIURA, Nobuyoshi SAITO, Tatsunori SAKANO, Tomomasa UEDA, Hajime YAMAGUCHI
  • Publication number: 20140084310
    Abstract: According to an embodiment, a method for manufacturing a display device, includes steps of disposing a cathode of a first substrate unit to face an anode of a second substrate unit with an intermediate layer interposed, and bonding the cathode to the anode with the intermediate layer interposed. The first substrate unit includes a first substrate, a thin film transistor provided on the first substrate, and the cathode connected to the thin film transistor. The thin film transistor is an n-channel thin film transistor. The second substrate unit includes a second substrate and the anode provided on the second substrate.
    Type: Application
    Filed: March 14, 2013
    Publication date: March 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro MIURA, Tomomasa Ueda, Nobuyoshi Saito, Shintaro Nakano, Tatsunori Sakano, Hajime Yamaguchi
  • Patent number: 8679904
    Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; source and drain electrodes provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source and drain electrodes above the gate electrode.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Shintaro Nakano, Shuichi Uchikoga
  • Publication number: 20140077204
    Abstract: According to one embodiment, a display device includes a first insulating layer, a second insulating layer, a pixel electrode, a light emitting layer, an opposite electrode and a pixel circuit. The second insulating layer is provided on the first insulating layer. The pixel electrode is provided on the second insulating layer and light-transmissive. The light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the light emitting layer. The circuit is provided between the first insulating layer and the second insulating layer, includes an interconnect supplied with a drive current, and is configured to supply the drive current to the pixel electrode. The circuit is connected to the pixel electrode. The interconnect has a first region overlaying the pixel electrode when projected onto a plane parallel to the first insulating layer. The interconnect has an opening in the first region.
    Type: Application
    Filed: March 4, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi SAITO, Tomomasa Ueda, Toshiya Yonehara, Hajime Yamaguchi, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano
  • Publication number: 20130313547
    Abstract: According to one embodiment, a display device includes a substrate, a thin film transistor, a pixel electrode, an organic light emitting layer, a common electrode, and a sealing unit. The thin film transistor is provided on the substrate. The thin film transistor includes a gate electrode, a gate insulating film, a semiconductor film, a first conducting portion, and a second conducting portion. The pixel electrode is electrically connected to one of the first conducting portion and the second conducting portion. The organic light emitting layer is provided on the pixel electrode. The common electrode is provided on the organic light emitting layer. The sealing unit is provided on the common electrode. The sealing unit includes a first sealing film and a second sealing film. A refractive index of the second sealing film is different from a refractive index of the first sealing film.
    Type: Application
    Filed: December 28, 2012
    Publication date: November 28, 2013
    Inventors: Shintaro NAKANO, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Hajime Yamaguchi
  • Publication number: 20130313545
    Abstract: According to one embodiment, a display device includes a substrate, a thin film transistor, a passivation film, a hydrogen barrier film, a pixel electrode, an organic light emitting layer, an opposite electrode, and a sealing film. The thin film transistor is provided on a major surface of the substrate. The thin film transistor includes a gate electrode, a gate insulating film, a semiconductor film, a first conducting portion, and a second conducting portion. The passivation film is provided on the thin film transistor. The hydrogen barrier film is provided on the passivation film. The pixel electrode is electrically connected to one of the first conducting portion and the second conducting portion. The organic light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the organic light emitting layer. The sealing film is provided on the hydrogen barrier film and the opposite electrode.
    Type: Application
    Filed: December 21, 2012
    Publication date: November 28, 2013
    Inventors: Nobuyoshi SAITO, Kentaro MIURA, Shintaro NAKANO, Tatsunori SAKANO, Tomomasa UEDA, Hajime YAMAGUCHI
  • Publication number: 20130302534
    Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.
    Type: Application
    Filed: July 17, 2013
    Publication date: November 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori SAKANO, Kentaro Miura, Nobuyoshi Saito, Shintaro Nakano, Tomomasa Ueda, Hajime Yamaguchi
  • Publication number: 20130277667
    Abstract: According to one embodiment, a display device includes a light transmissive substrate, a light transmissive pixel electrode, a switching element, an organic light emitting layer, a light transmissive opposite electrode, a conductive light absorption layer and a conductive film. The light transmissive pixel electrode is provided on the substrate. The switching element is provided on the substrate and electrically connected to the pixel electrode. The organic light emitting layer is provided on the pixel electrode. The light transmissive opposite electrode is provided on the organic light emitting layer. The conductive light absorption layer is provided on the opposite electrode. The conductive film is provided on the light absorption layer.
    Type: Application
    Filed: September 19, 2012
    Publication date: October 24, 2013
    Inventors: Nobuyoshi SAITO, Kentaro Miura, Tomomasa Ueda, Shintaro Nakano, Tatsunori Sakano, Hajime Yamaguchi
  • Publication number: 20130277646
    Abstract: According to one embodiment, a display panel includes a substrate, a switching element, a pixel electrode, an organic light emitting layer, an opposite electrode, a detecting electrode, and an insulating layer. The substrate has a major surface. The switching element is provided on the major surface. The switching element includes a semiconductor layer. The pixel electrode is provided on the major surface. The pixel electrode is electrically connected to the switching element. The organic light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the organic light emitting layer. The detecting electrode is provided between the substrate and at least a part of the pixel electrode. The detecting electrode includes at least one element included in the semiconductor layer. The insulating layer is provided between the pixel electrode and the detecting electrode.
    Type: Application
    Filed: December 20, 2012
    Publication date: October 24, 2013
    Inventors: Nobuyoshi SAITO, Tomomasa Ueda, Hajime Yamaguchi, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano
  • Patent number: 8525182
    Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; a source electrode and a drain electrode provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source electrode and the drain electrode above the gate electrode.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Shintaro Nakano, Shuichi Uchikoga
  • Patent number: 8513040
    Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Sakano, Kentaro Miura, Nobuyoshi Saito, Shintaro Nakano, Tomomasa Ueda, Hajime Yamaguchi
  • Publication number: 20130078752
    Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.
    Type: Application
    Filed: May 30, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori SAKANO, Kentaro MIURA, Nobuyoshi SAITO, Shintaro NAKANO, Tomomasa UEDA, Hajime YAMAGUCHI
  • Publication number: 20130075719
    Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
    Type: Application
    Filed: May 30, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Tomomasa UEDA, Kentaro MIURA, Nobuyoshi SAITO, Tatsunori SAKANO, Hajime YAMAGUCHI
  • Publication number: 20120242562
    Abstract: According to one embodiment, a display device includes an insulating layer, a display unit, and an organic EL layer. The display unit is provided on a major surface of the insulating layer and includes a plurality of gate lines, a plurality of signal lines, a plurality of power source lines and a plurality of pixel units arranged in a matrix configuration. The EL layer is provided on the display unit. Each pixel unit includes a drive transistor and a resistor. The drive transistor includes a drive gate electrode, a drive source electrode, and a drive drain electrode. The drive source electrode or the drive drain electrode is connected to one of the power source lines. An end of the resistor is connected to the drive gate electrode. An other end of the resistor is connected to one of the gate line, the signal line, and the power source line.
    Type: Application
    Filed: September 21, 2011
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi SAITO, Tomomasa Ueda, Hajime Yamaguchi, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano
  • Publication number: 20120223301
    Abstract: According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: September 6, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomomasa Ueda, Shintaro Nakano, Nobuyoshi Saito, Kentaro Miura, Yujiro Hara, Hajime Yamaguchi
  • Publication number: 20120211745
    Abstract: According to one embodiment, a thin film transistor includes a gate electrode, a semiconductor layer, a gate insulating film, and a source electrode and a drain electrode. The semiconductor layer includes an oxide including at least one of gallium and zinc, and indium. The gate insulating film is provided between the gate electrode and the semiconductor layer. The source electrode and a drain electrode are electrically connected to the semiconductor layer and spaced from each other. The semiconductor layer includes a plurality of fine crystallites dispersed three-dimensionally in the semiconductor layer and has periodicity in arrangement of atoms.
    Type: Application
    Filed: March 2, 2012
    Publication date: August 23, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Shintaro Nakano, Nobuyoshi Saito, Yujiro Hara, Shuichi Uchikoga