Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a gate insulating film on a semiconductor layer; an oxide semiconductor layer above the semiconductor layer; a first control gate of a first cell and a second control gate of a second cell on an insulating layer on the oxide semiconductor layer; a third gate of a first transistor between the first control gate and the second control gate; a fourth gate of a second transistor between a first end of the oxide semiconductor layer and the second control gate; an interconnect connected to the first end; a source line connected to the first select transistor; and a bit line connected to the second select transistor.

Abstract: According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.

Abstract: According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.

Abstract: According to one embodiment, a method for manufacturing a display element is disclosed. The method can include forming a peeling layer, forming a resin layer, forming a barrier layer, forming an interconnect layer, forming a display layer, and removing. The peeling layer is formed on a major surface of a base body. The major surface has first, second, and third regions. The peeling layer includes first, second, and third peeling portions. The resin layer is formed on the peeling layer. The resin layer includes first and second resin portions. The barrier layer is formed on the first, second, and third peeling portions. The interconnect layer is formed on the barrier layer. The display layer is formed on the interconnect layer. The first peeling portion is removed from the first resin portion and the second peeling portion is removed from the second resin portion.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion, a first gate electrode, a second gate electrode, an insulating film. The first semiconductor portion includes a first portion, a second portion and a third portion provided between the first portion and the second portion. The second semiconductor portion includes a fourth portion separated from the first portion, a fifth portion separated from the second portion, and a sixth portion provided between the forth portion and the fifth portion. The first gate electrode is separated from the third portion. The second gate electrode is separated from the sixth portion. The insulating film is provided at a first position between the first gate electrode and the semiconductor layer and at a second position between the second gate electrode and the semiconductor layer.

Abstract: According to an embodiment, an input device includes the following elements. The flexible touch panel includes a sensor area. The touch position detector detects a touch position on the sensor area to generate a detection signal. The deformation position detector detects a deformation position where a deformation amount is not less than a threshold on the sensor area. The input rejection area determination unit determines, based on the deformation position, an input rejection area. The input signal generator fails to output the detection signal as an input signal if the touch position is detected in the input rejection area, and outputs the detection signal as an input signal if the touch position is detected in an area other than the input rejection area.

Abstract: According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.

Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.

Abstract: A semiconductor element includes a semiconductor layer, a first and a second conductive unit, a gate electrode, and a gate insulating film. The semiconductor layer includes a first portion, a second portion, and a third portion provided between the first portion and the second portion. The first conductive unit is electrically connected to the first portion. The second conductive unit is electrically connected to the second portion. The gate electrode is separated from the first conductive unit, the second conductive unit, and the third portion. The gate electrode opposes the third portion. The gate insulating film is provided between the third portion and the gate electrode. A concentration of nitrogen of the first portion is higher than a concentration of nitrogen of the third portion. A concentration of nitrogen of the second portion is higher than the concentration of nitrogen of the third portion.

Abstract: According to one embodiment, a thin film transistor includes a first insulating film, a gate electrode, a semiconductor layer, a gate insulator film, a second insulating film, a source electrode, a tunneling insulating portion, and a drain electrode. The semiconductor layer is provided between the gate electrode and the first insulating film, and includes an amorphous oxide. The gate insulator film is provided between the semiconductor layer and the gate electrode. The second insulating film is provided between the semiconductor layer and the first insulating film. The tunneling insulating portion is provided between the semiconductor layer and the source electrode, and between the semiconductor layer and the drain electrode, and between the first insulating film and the second insulating film. The tunneling insulating portion includes oxygen and at least one selected from aluminum and magnesium. A thickness of the tunneling insulating portion is 2 nanometers or less.

Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.

Abstract: According to one embodiment, a thin film transistor includes a gate electrode, a semiconductor layer, a gate insulating film, and a source electrode and a drain electrode. The semiconductor layer includes an oxide including at least one of gallium and zinc, and indium. The gate insulating film is provided between the gate electrode and the semiconductor layer. The source electrode and a drain electrode are electrically connected to the semiconductor layer and spaced from each other. The semiconductor layer includes a plurality of fine crystallites dispersed three-dimensionally in the semiconductor layer and has periodicity in arrangement of atoms.

Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.

Abstract: According to one embodiment, a display panel includes a substrate, a switching element, a pixel electrode, an organic light emitting layer, an opposite electrode, a detecting electrode, and an insulating layer. The substrate has a major surface. The switching element is provided on the major surface. The switching element includes a semiconductor layer. The pixel electrode is provided on the major surface. The pixel electrode is electrically connected to the switching element. The organic light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the organic light emitting layer. The detecting electrode is provided between the substrate and at least a part of the pixel electrode. The detecting electrode includes at least one element included in the semiconductor layer. The insulating layer is provided between the pixel electrode and the detecting electrode.