Patents by Inventor Tomomasa Ueda

Tomomasa Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6797536
    Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: September 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Minoru Amano, Tatsuya Kishi, Keiji Hosotani, Junichi Miyamoto
  • Publication number: 20040179393
    Abstract: A write wiring for writing information in an MTJ device is covered with a magnetic layer. The magnetic layer has a structure in which the growing direction of columnar grains is 30° or less from the normal-line direction of sidewalls, a structure in which grains are deposited like a layer, or a structure in which grains are amorphously deposited.
    Type: Application
    Filed: September 29, 2003
    Publication date: September 16, 2004
    Inventors: Hiroaki Yoda, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20040156232
    Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first wiring extending in a first direction on or below the magnetoresistance effect element; a covering layer provided at least both sides of the first wiring, the covering layer being made of magnetic material, and the covering layer having a uniaxial anisotropy in the first direction along which a magnetization of the covering layer occurs easily; and a writing circuit configured to pass a current through the first wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.
    Type: Application
    Filed: February 3, 2004
    Publication date: August 12, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Saito, Katsuya Nishiyama, Shigeki Takahashi, Minoru Amano, Tomomasa Ueda, Hiroaki Yoda, Yoshiaki Asao, Yoshihisa Iwata, Tatsuya Kishi
  • Publication number: 20040152227
    Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 5, 2004
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Minoru Amano, Tatsuya Kishi, Keiji Hosotani, Junichi Miyamoto
  • Patent number: 6765824
    Abstract: There is provided a magnetoresistance element in which a shape of a free ferromagnetic layer includes a first portion with a parallelogrammic contour, and second portions that protrude from a pair of opposite corners of the first portion respectively in a main direction parallel to a pair of opposite sides of the first portion, the shape is asymmetric with respect to a line that passes through a center of the first portion and is parallel to the main direction, and an axis of easy magnetization of the free ferromagnetic layer falls within a range defined by an acute angle that a first direction makes with a second direction, the first direction being substantially parallel to the main direction and the second direction being substantially parallel to the longest line segment that joins contours of the second portions.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: July 20, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Kishi, Yoshiaki Saito, Minoru Amano, Shigeki Takahashi, Katsuya Nishiyama, Tomomasa Ueda
  • Patent number: 6765821
    Abstract: There are provided at least one wire, a magnetoresistive effect element having a storage layer whose magnetization direction varies according to a current magnetic field generated by causing a current to flow in the wire, and first yokes provided so as to be spaced from at least one pair of opposed side faces of the magnetoresistive effect element to form a magnetic circuit in cooperation with the magnetoresistive effect element when a current is caused to flow in the wire. Each of the first yokes has at least two soft magnetic layers which are stacked via a non-magnetic layer.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: July 20, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Tomomasa Ueda, Tatsuya Kishi, Minoru Amano
  • Publication number: 20040100818
    Abstract: A write line is covered with a yoke material. The recording layer of an MTJ element is exchange-coupled to the yoke material. The total magnetic volume &Sgr;Msi×ti of the recording layer of the MTJ element and a portion of the yoke material that is exchange-coupled to the recording layer is smaller than the magnetic volume &Sgr;Msi′×ti′ of the remaining portion of the yoke material that covers the write line.
    Type: Application
    Filed: March 6, 2003
    Publication date: May 27, 2004
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Junichi Miyamoto, Tatsuya Kishi, Minoru Amano, Takeshi Kajiyama, Hisanori Aikawa
  • Publication number: 20040076035
    Abstract: There are provided at least one wire, a magnetoresistive effect element having a storage layer whose magnetization direction varies according to a current magnetic field generated by causing a current to flow in the wire, and first yokes provided so as to be spaced from at least one pair of opposed side faces of the magnetoresistive effect element to form a magnetic circuit in cooperation with the magnetoresistive effect element when a current is caused to flow in the wire. Each of the first yokes has at least two soft magnetic layers which are stacked via a non-magnetic layer.
    Type: Application
    Filed: September 16, 2003
    Publication date: April 22, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Saito, Tomomasa Ueda, Tatsuya Kishi, Minoru Amano
  • Patent number: 6717845
    Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first wiring extending in a first direction on or below the magnetoresistance effect element; a covering layer provided at least both sides of the first wiring, the covering layer being made of magnetic material, and the covering layer having a uniaxial anisotropy in the first direction along which a magnetization of the covering layer occurs easily; and a writing circuit configured to pass a current through the first wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: April 6, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Katsuya Nishiyama, Shigeki Takahashi, Minoru Amano, Tomomasa Ueda, Hiroaki Yoda, Yoshiaki Asao, Yoshihisa Iwata, Tatsuya Kishi
  • Publication number: 20040021189
    Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.
    Type: Application
    Filed: March 6, 2003
    Publication date: February 5, 2004
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Minoru Amano, Tatsuya Kishi, Keiji Hosotani, Junichi Miyamoto
  • Publication number: 20040004889
    Abstract: A write word line is disposed right under an MTJ element. The write word line extends in an X direction, and a lower surface of the line is coated with a yoke material which has a high permeability. A data selection line (read/write bit line) is disposed right on the MTJ element. A data selection line extends in a Y direction intersecting with the X direction, and an upper surface of the line is coated with the yoke material which has the high permeability. At a write operation time, a magnetic field generated by a write current flowing through a write word line B and data selection line functions on the MTJ element by the yoke material with good efficiency.
    Type: Application
    Filed: April 18, 2003
    Publication date: January 8, 2004
    Inventors: Yoshiaki Asao, Yoshihisa Iwata, Yoshiaki Saito, Hiroaki Yoda, Tomomasa Ueda, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi
  • Publication number: 20030214862
    Abstract: A write word line is disposed right under a MTJ element. The write word line extends in an X direction, and side and lower surfaces of the write word line are coated with a hard magnetic material and yoke material. The hard magnetic material is magnetized by a surplus current passed through the write word line, and a characteristic of the MTJ element is corrected by residual magnetization. A data selection line (read/write bit line) is disposed right on the MTJ element. The data selection line extends in a Y direction intersecting with the X direction, and a part of the surface of the data selection line is coated with the yoke material.
    Type: Application
    Filed: April 22, 2003
    Publication date: November 20, 2003
    Inventors: Yoshiaki Asao, Yoshihisa Iwata, Yoshiaki Saito, Hiroaki Yoda, Tomomasa Ueda, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi
  • Publication number: 20030186552
    Abstract: There is provided a magnetic memory device which has a small switching current for a writing line and which has a small variation therein. A method for producing such a magnetic memory device includes: forming a magnetoresistive effect element; forming a first insulating film so as to cover the magnetoresistive effect element; forming a coating film so as to cover the first insulating film; exposing a top face of the magnetoresistive effect element; forming an upper writing line on the magnetoresistive effect element; exposing the first insulating film on a side portion of the magnetoresistive effect element by removing a part or all of the coating film; and forming a yoke structural member so as to cover at least a side portion of the upper writing line and so as to contact the exposed first insulating film on the side portion of the magnetoresistive effect element.
    Type: Application
    Filed: March 26, 2003
    Publication date: October 2, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Minoru Amano, Tatsuya Kishi, Yoshiaki Saito, Tomomasa Ueda, Hiroaki Yoda
  • Publication number: 20030185050
    Abstract: There is provided a magnetoresistance element in which a shape of a free ferromagnetic layer includes a first portion with a parallelogrammic contour, and second portions that protrude from a pair of opposite corners of the first portion respectively in a main direction parallel to a pair of opposite sides of the first portion, the shape is asymmetric with respect to a line that passes through a center of the first portion and is parallel to the main direction, and an axis of easy magnetization of the free ferromagnetic layer falls within a range defined by an acute angle that a first direction makes with a second direction, the first direction being substantially parallel to the main direction and the second direction being substantially parallel to the longest line segment that joins contours of the second portions.
    Type: Application
    Filed: March 19, 2003
    Publication date: October 2, 2003
    Inventors: Tatsuya Kishi, Yoshiaki Saito, Minoru Amano, Shigeki Takahashi, Katsuya Nishiyama, Tomomasa Ueda
  • Publication number: 20030161181
    Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first wiring extending in a first direction on or below the magnetoresistance effect element; a covering layer provided at least both sides of the first wiring, the covering layer being made of magnetic material, and the covering layer having a uniaxial anisotropy in the first direction along which a magnetization of the covering layer occurs easily; and a writing circuit configured to pass a current through the first wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.
    Type: Application
    Filed: January 16, 2003
    Publication date: August 28, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Saito, Katsuya Nishiyama, Shigeki Takahashi, Minoru Amano, Tomomasa Ueda, Hiroaki Yoda, Yoshiaki Asao, Yoshihisa Iwata, Tatsuya Kishi
  • Publication number: 20030156476
    Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.
    Type: Application
    Filed: January 16, 2003
    Publication date: August 21, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Kishi, Minoru Amano, Yoshiaki Saito, Shigeki Takahashi, Katsuya Nishiyama, Yoshiaki Asao, Hiroaki Yoda, Tomomasa Ueda, Yoshihisa Iwata
  • Publication number: 20030123283
    Abstract: A highly reliable magnetic memory exhibits enhanced data-holding stability at high storage density in a storage layer of a magnetoresistive effect element used for memory cells. A magnetic memory includes a memory cell array having first wirings, second wirings intersecting the first wirings and memory cells each provided at an intersection area of the corresponding first and second wirings. Each memory cell is selected when the corresponding first and second wirings are selected.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 3, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Minoru Amano, Tatsuya Kishi, Hiroaki Yoda, Yoshiaki Saito, Shigeki Takahashi, Tomomasa Ueda, Katsuya Nishiyama, Yoshiaki Asao, Yoshihisa Iwata
  • Patent number: 6078365
    Abstract: An active matrix liquid crystal panel includes a plurality of thin film transistors respectively arranged adjacent to pixel electrodes, and a plurality of auxiliary capacitances. Each transistor has a semiconductor active layer, a pair of source and drain electrodes, and a gate electrode opposing the active layer via a gate insulating film. Each auxiliary capacitance has upper and lower electrodes, and a dielectric layer sandwiched between the upper and lower electrodes. The gate electrode, the lower electrode, and an address line respectively have portions formed of a common refractory metal film arranged on the insulating surface of a support substrate. The source and drain electrodes, the upper electrode, and a signal line respectively have portions formed of a common Mo film. Each pixel electrode has a portion formed of an ITO film. Each auxiliary capacitance further has an intervening layer between the dielectric layer and the upper electrode.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: June 20, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Yutaka Onozuka, Yujiro Hara, Shuichi Saito, Mitsushi Ikeda
  • Patent number: 5600461
    Abstract: An active matrix type liquid crystal display device having an array substrate for allowing parasitic capacitances formed between a pixel electrode and scan and signal lines disposed in the vicinity thereof to be remarkably decreased.
    Type: Grant
    Filed: June 14, 1995
    Date of Patent: February 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Masahiko Akiyama, Atsushi Sugahara, Makoto Shibusawa, Mitsushi Ikeda, Yoshiko Tsuji, Hisao Toeda
  • Patent number: 5459596
    Abstract: An active matrix type liquid crystal display device having a plurality of scan lines, a plurality of signal lines intersected with the plurality of scan lines, the plurality of scan lines being insulated from the plurality of signal lines, a thin film transistor element having a gate portion and a drain portion and disposed at each intersection of the plurality of scan lines and the plurality of signal lines, the gate portion being connected to a scan line at the intersection, the drain portion being connected to a signal line at the intersection, an array substrate formed in the intersection and having a pixel electrode, the pixel electrode being electrically connected to the source portion of the thin film transistor element, an opposite substrate having an opposite electrode opposed to the array substrate, a liquid crystal layer disposed between the array substrate and the opposite substrate, and a shield electrode disposed on the array substrate, the shield electrode being overlaid through an insulation l
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: October 17, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Masahiko Akiyama, Atsushi Sugahara, Makoto Shibusawa, Mitsushi Ikeda, Yoshiko Tsuji, Hisao Toeda