Abstract: Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics.

Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

Abstract: To realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics a semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that at the time of writing, the assist electrode is used as an assist electrode for hot electrons to be injected at the source side and at the time of reading, an inversion layer formed under the assist electrode is used as the source region or the drain region.

Abstract: An electrode drive circuit performs interlaced scanning, ensuring that the phases of the sustaining pulse in odd-numbered lines and even-numbered lines among L1 to L8 between surface discharge electrodes are the reverse of each other. With this, when either odd-numbered lines or even-numbered lines are displayed, the voltages applied between the electrodes of the undisplayed lines are at 0, eliminating the necessity for partitioning walls on the surface discharge electrodes. In surface discharge electrodes, X electrodes are provided on the two sides of a Y electrode and the area between the Y electrode and the X electrode on one side is assigned a display line at an odd-numbered frame, and the area between the Y electrode and the X electrode on the other side is assigned a display line in an even-numbered frame.

Abstract: A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

Abstract: An image scanning apparatus includes a reader which reads an original document in accordance with a first reading condition and generates a first image data corresponding to the original document, a processor which calculates a first calculated value relating to a first attribution of the first image data and a second supposed value based on a second reading condition different from the first reading condition and one of the first image data and the first calculated value, wherein the second supposed value relates to a second attribution, and the second attribution relates to a second image data which are generated in case the original document, is read in accordance with the second reading condition, and a display which displays the first calculated value and the second supposed value.

Abstract: Disclosed is a light-intensity modulation element, which comprises a substrate made of a nonlinear optical crystal, and a light waveguide formed in a principal surface of the substrate to extend in one direction. The light waveguide includes first and second wavelength conversion portions for converting a part of infrared light introduced into the light waveguide to a second harmonic. Each of the first and second wavelength conversion portions has a plurality of polarization structures serially disposed in the longitudinal direction of the light waveguide in such a manner that their polarities in the thickness direction of the substrate are inverted periodically and alternately in the longitudinal direction of the light waveguide. The light waveguide further includes a phase adjustment portion located between the first and second wavelength conversion portions, and associated with a pair of electrodes disposed in opposed relation to one another on opposite sides thereof.

Abstract: The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.

Abstract: Method for driving a plasma display panel. At least one first discharge sustaining pulse is applied to a first pair of display electrodes, and at least one second discharge sustaining pulse applied to an adjacent pair of display electrodes. The first and second discharge sustaining pulses are applied such that they are in the same phase as one another and/or such that a current in the first pair of display electrodes flows in the opposite direction from a current in the adjacent pair of display electrodes.

Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Abstract: A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure. The conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.

Abstract: A nonvolatile semiconductor memory device that uses inversion layers formed on a surface of its semiconductor substrate as data lines, which is capable of satisfying the requirements of suppressing both characteristic variation among memory cells and bit cost. In order to achieve the above object, in the memory device, a plurality of assist gates are formed so as to be embedded in a p-type well via a silicon oxide film, respectively and silicon nanocrystal grains of about 6 nm in average diameter used for storing information are formed without being in contact with one another. Then, a plurality of word lines are formed practically in a direction vertically to the assist gates and the space between adjacent those of the plurality of word lines is set under ½ of the width (gate length) of the word lines.

Abstract: A data processor includes an authentication function for judging access right. The data processor further includes a nonvolatile memory cell array formed on an insulator film or a chip, and a conductor layer provided between a logic circuit for the authentication and the nonvolatile memory. The nonvolatile memory can store at least part of authentication information or an authentication program.

Abstract: A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

Abstract: A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most.

Abstract: In a semiconductor flash memory required to have high reliability, injection and extraction of electrons must be performed through an oxide film obtained by directly oxidizing a silicon substrate. Accordingly, the voltage to be used is a large voltage ranging from positive to negative one. In contrast, by storing charges in a plurality of dispersed regions, high reliability is achieved. Based on the high reliability, transfer of electrons is permitted through not only the oxide film obtained by directly thermally oxidizing a high reliability silicon substrate but also another oxide film deposited by CVD, or the like. In consequence, a device is controlled by electric potentials of the same polarity upon writing of data and upon erasing of data.

Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

Abstract: A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noises. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions.