Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode disposed over the semiconductor substrate and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate between the gate electrode and the dummy gate electrode, and a conductor electrically connecting the first semiconductor area with the dummy gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode disposed over the semiconductor substrate and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate between the gate electrode and the dummy gate electrode, and a conductor electrically connecting the first semiconductor area with the dummy gate electrode.

Abstract: A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing.

Abstract: A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode.

Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.

Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.

Abstract: A method of manufacturing a semiconductor device comprises forming a first insulator in the first area of a substrate and a second insulator formed in a second area of the substrate; forming an etching preventing film extending over the first device region surrounded by the first area and the second device region surrounded by the second area removing the etching preventing film from the first device region and first area forming a first gate insulating film over the first device region while the second device region and the second area are covered by the etching preventing film; removing the etching preventing film over the second device region and the second area forming a second gate insulating film over the second device region; and forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first area; removing the oxidation film over the first device region, forming a first gate insulating film over the first device region, removing the oxidation film over the second device region, forming a second gate insulating film over the second device region, forming a first gate electrode over the first gate insulating film, forming a second gate electrode over the second gate insulating film, forming first source and drain regions in the first device region at both sides of the first gate electrode, and forming second source and drain regions in the second device region at both sides of the second gate electrode.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: A semiconductor device includes a first gate insulating film over a first device region, a second gate insulating film over a second device region, a first gate electrode over the first gate insulating film, a second gate electrode over the second gate insulating film, first source and drain regions in the first device region at both sides of the first gate electrode, second source and drain regions in the second device region at both sides of the second gate electrode, and a memory cell memory cell that further includes a tunnel insulating film formed over a third device region, a floating gate formed over the tunnel insulating film, an insulating film formed over the floating gate, a control gate formed over the tunnel insulating film, and third source and drain regions formed in third device region at both sides of the floating gate and the control gate.

Abstract: A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film.

Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.

Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.

Abstract: A method of manufacturing a semiconductor device including a stacked gate type nonvolatile memory cell and a p-channel type first transistor, includes: forming a gate insulating film of the first transistor on a semiconductor substrate; forming a tunnel insulating film of the stacked gate type nonvolatile memory cell on the semiconductor substrate; forming a first conductive layer containing an n-type impurity on the tunnel insulating film and the gate insulating film; and implanting p-type impurity ions to a region of the first conductive layer for forming the first transistor to turn the region of the first conductive layer into a p-type region.

Abstract: A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make the second conductive film into a second conductor; forming an interlayer insulating film (a third insulating film) covering the second conductor; forming a first hole in the interlayer insulating film on the contact region; and forming a conductive plug, which is electrically connected with the contact region, in the first hole.

Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.