Patents by Inventor Toru Anezaki
Toru Anezaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20120034751Abstract: A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.Type: ApplicationFiled: May 12, 2011Publication date: February 9, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Junichi Ariyoshi, Taiji Ema, Toru Anezaki
-
Patent number: 8080852Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: GrantFiled: December 10, 2010Date of Patent: December 20, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
-
Publication number: 20110278659Abstract: A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first area; removing the oxidation film over the first device region, forming a first gate insulating film over the first device region, removing the oxidation film over the second device region, forming a second gate insulating film over the second device region, forming a first gate electrode over the first gate insulating film, forming a second gate electrode over the second gate insulating film, forming first source and drain regions in the first device region at both sides of the first gate electrode, and forming second source and drain regions in the second device region at both sides of the second gate electrode.Type: ApplicationFiled: July 8, 2011Publication date: November 17, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Toru Anezaki
-
Publication number: 20110254074Abstract: A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode.Type: ApplicationFiled: March 30, 2011Publication date: October 20, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Toru Anezaki
-
Publication number: 20110198707Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500 ° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.Type: ApplicationFiled: March 30, 2011Publication date: August 18, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji EMA, Hideyuki KOJIMA, Toru ANEZAKI
-
Patent number: 7998806Abstract: A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first area; removing the oxidation film over the first device region, forming a first gate insulating film over the first device region, removing the oxidation film over the second device region, forming a second gate insulating film over the second device region, forming a first gate electrode over the first gate insulating film, forming a second gate electrode over the second gate insulating film, forming first source and drain regions in the first device region at both sides of the first gate electrode, and forming second source and drain regions in the second device region at both sides of the second gate electrode.Type: GrantFiled: August 7, 2008Date of Patent: August 16, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Toru Anezaki
-
Publication number: 20110111567Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: ApplicationFiled: January 20, 2011Publication date: May 12, 2011Applicant: FUJITSU LIMITEDInventors: Tomohiko TSUTSUMI, Taiji EMA, Hideyuki KOJIMA, Toru ANEZAKI
-
Publication number: 20110108925Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: ApplicationFiled: January 20, 2011Publication date: May 12, 2011Applicant: FUJITSU LIMITEDInventors: Tomohiko TSUTSUMI, Taiji Ema, Hideyuki Kojima, Toru Anezaki
-
Patent number: 7939893Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.Type: GrantFiled: August 11, 2010Date of Patent: May 10, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
-
Patent number: 7936579Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: June 2, 2010Date of Patent: May 3, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
-
Publication number: 20110073950Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: ApplicationFiled: December 10, 2010Publication date: March 31, 2011Applicant: FUJITSU LIMITEDInventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
-
Patent number: 7888740Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: GrantFiled: November 21, 2007Date of Patent: February 15, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
-
Publication number: 20100320543Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.Type: ApplicationFiled: August 11, 2010Publication date: December 23, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji EMA, Hideyuki KOJIMA, Toru ANEZAKI
-
Publication number: 20100238716Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: ApplicationFiled: June 2, 2010Publication date: September 23, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
-
Patent number: 7795100Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.Type: GrantFiled: July 15, 2008Date of Patent: September 14, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Hedeyuki Kojima, Toru Anezaki
-
Patent number: 7755928Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: February 6, 2009Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
-
Patent number: 7723825Abstract: According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.Type: GrantFiled: October 30, 2006Date of Patent: May 25, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Masayoshi Asano, Toru Anezaki, Junichi Ariyoshi
-
Publication number: 20100105180Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.Type: ApplicationFiled: December 31, 2009Publication date: April 29, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
-
Patent number: 7671384Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.Type: GrantFiled: August 24, 2005Date of Patent: March 2, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
-
Patent number: 7605041Abstract: Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.Type: GrantFiled: December 7, 2007Date of Patent: October 20, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki