Abstract: A manufacturing method of a substrate unit includes forming a semiconductor laminated body on a substrate; forming a sacrificial layer on the semiconductor laminated body; forming a semiconductor functional layer on the sacrificial layer; and forming a protective film that covers at least a back surface of the substrate different from a formation surface on which the semiconductor laminated body is formed, a side face of the substrate, and a side face of the semiconductor laminated body.

Abstract: According to an embodiment, a semiconductor device includes a conductive layer, a semiconductor portion, a first source electrode, a second source electrode, a first control electrode, and a first control electrode. The semiconductor portion is provided on the conductive layer. The semiconductor portion has a first element region and a second element region. A first end portion of the conductive layer is located inside a second end portion of the semiconductor portion in a plan view. An outer periphery formed by the first end portion surrounds both at least a part of a third end portion of the first element region and at least a part of a fourth end portion of the second element region.

Abstract: The present invention is a surface-modified carbon material including chemical addends added to the surface of graphene, such that a one-dimensional periodicity corresponding to a large number of addition positions of the chemical addends can be observed in a Fourier-transformed image of a scanning probe microscopic image of the surface of graphene. The surface-modified carbon material of the present invention has a bandgap and therefore can be used as a sensor capable of electronically controlling an operation or another electronic device.

Abstract: A liquid discharging apparatus includes an accommodating container accommodating conductive liquid, a rod-shaped first electrode accommodated in the accommodating container, a rod-shaped second electrode accommodated in the accommodating container, a detection portion that is electrically coupled to the first electrode and the second electrode and that detects a remaining amount of the liquid accommodated in the accommodating container in response to an electric signal from at least one of the first electrode and the second electrode, and a liquid discharging head discharging the liquid that is supplied from the accommodating container, in which the first electrode includes a first part having an outer periphery with a first length, and a second part having an outer periphery with a second length that is shorter than the first length.

Abstract: A liquid discharging apparatus includes an accommodating container accommodating conductive liquid, a first electrode accommodated in the accommodating container, a second electrode accommodated in the accommodating container, a detection portion that is electrically coupled to the first electrode and the second electrode and that detects a remaining amount of the liquid accommodated in the accommodating container in response to an electric signal from at least one of the first electrode and the second electrode, and a liquid discharging head discharging the liquid that is supplied from the accommodating container, in which the first electrode includes a first part where a distance between the first part and the second electrode is a first distance, and a second part where a distance between the second part and the second electrode is a second distance that is longer than the first distance.

Abstract: A liquid ejecting apparatus includes: a container that contains a liquid having conductivity; an electrode bar that is disposed inside the container and that includes a first terminal, a second terminal, and a first insulating section that electrically insulates the first terminal from the second terminal; a detection section that detects a remaining amount of liquid contained in the container in accordance with an electrical signal from at least one of the first terminal and the second terminal; and a liquid ejection head that discharges the liquid supplied from the container. The remaining amount of liquid detected by the detection section when the first terminal is electrically coupled to the second terminal via the liquid in the container is larger than the remaining amount of liquid detected by the detection section when the first terminal is not electrically coupled to the second terminal via the liquid in the container.

Abstract: A liquid accommodating device includes an accommodating container accommodating conductive liquid, a first electrode accommodated in the accommodating container, a second electrode accommodated in the accommodating container, and a detection portion that is electrically coupled to the first electrode and the second electrode and that detects a remaining amount of the liquid accommodated in the accommodating container in response to an electric signal from at least one of the first electrode and the second electrode, in which the first electrode includes a first part where a first conduction portion formed with a conductive member is exposed, a second part where the first conduction portion is exposed, and a first insulation part that is provided between the first part and the second part and in which the first conduction portion is covered with an insulation member.

Abstract: A plasma processing apparatus in the present disclosure includes a plasma processing chamber, a gas supply, a power supply, and a controller. The controller causes (a) forming a first film on side walls of an opening of a processing target using the plasma so that the first film has different thicknesses along a spacing between pairs of side walls facing each other, and (b) forming a second film by performing a film forming cycle one or more times after (a) so that the second film has different thicknesses along the spacing between the pairs of side walls facing each other.

Abstract: A substrate processing apparatus includes a chamber; a substrate support disposed in the chamber; a gas supply that supplies a gas into the chamber; and a controller that controls an overall operation of the substrate processing apparatus. The controller executes a process including: (a) placing a substrate on the substrate support, the substrate including an etching layer and a patterned mask on the etching layer; (b) forming a film on the patterned mask; (c) forming a reaction layer on the film; and (d) removing the reaction layer by applying energy to the reaction layer. In the step (c) a temperature of the substrate is set according to a thickness of the reaction layer to be formed.

Abstract: The present invention is a surface-modified carbon material including chemical addends added to the surface of graphene, such that a one-dimensional periodicity corresponding to a large number of addition positions of the chemical addends can be observed in a Fourier-transformed image of a scanning probe microscopic image of the surface of graphene. The surface-modified carbon material of the present invention has a bandgap and therefore can be used as a sensor capable of electronically controlling an operation or another electronic device.

Abstract: An apparatus includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit which is configured to activate first and second internal signals in a time-division manner in response to a first external command A first number of the word lines arc selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal. The second number is smaller than the first number.

Abstract: Apparatuses and methods for 1T and 2T memory cell architectures. A memory array includes a word line which has both 1T and 2T portions. In the 1T portion, each sense amplifier is coupled to one memory cell along the word line. In the 2T portion, sense amplifiers are coupled to more than one memory cell along the word line each. For example, each sense amplifier in the 2T portion may be coupled to two bit lines, each of which intersect a memory cell along the word line. In some embodiments, the 2T portion may store a count value which represents an access count to the word line.

Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods are disclosed. An apparatus includes a first output terminal electrically connected to a pull-up gate terminal of at least one pull-up SCRC transistor and a second output terminal electrically connected to a pull-down gate terminal of at least one pull-down SCRC transistor. The apparatus also includes a first resistive path between a first input terminal and the first output terminal and a second resistive path between the second input terminal and the second output terminal. The apparatus further includes a charge transfer gate electrically connected between the first resistive path and the second resistive path.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: An error correction code (ECC) circuit receives a plurality of data hits and provides a one or more parity bits. The parity bits are used to locate and/or correct errors in the data bits. The ECC circuit splits the plurality of data bits into multiple portions and then processes these portions sequentially to generate preliminary parity bits. Once the portions of the data have been sequentially processed, the preliminary parity bits are combined to generate the parity bits.

Abstract: Apparatuses and methods for 1T and 2T memory cell architectures. A memory array includes a word line which has both 1T and 2T portions. In the 1T portion, each sense amplifier is coupled to one memory cell along the word line. In the 2T portion, sense amplifiers are coupled to more than one memory cell along the word line each. For example, each sense amplifier in the 2T portion may be coupled to two bit lines, each of which intersect a memory cell along the word line. In some embodiments, the 2T portion may store a count value which represents an access count to the word line.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.

Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.

Abstract: Apparatuses, systems, and methods for error correction for selected bit pairs. A memory device may include an error correction code (ECC) circuit which may receive data bits as part of a read or write operation and generate parity bits based on the data bits. The parity bits may be used to locate and correct errors in the data bits. The parity bits may be generated based on a syndrome value. Each of the individual data bits may be associated with a syndrome value. In addition, some selected pairs of data bits may also be associated. with a syndrome value. This may allow the ECC circuit to correct errors in individual data bits or in one of the selected pairs of data bits. In some embodiments, the selected pairs may represent adjacent memory cells along a word line.