Patents by Inventor Toru Ishikawa

Toru Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220182105
    Abstract: A signal processing device includes: a first subarray that includes power amplifiers and phase shifters and that forms a first beam facing in a first direction; a second subarray that includes power amplifiers and phase shifters and that forms a second beam facing in a second direction; a feedback unit that feeds back at least signals that are output from the power amplifiers included in the first subarray; and a processor that is connected to the first subarray and the second subarray. The processor executes a process including: generating, based on a first feedback signal and a transmission signal output to the first subarray, a cancellation signal corresponding to an interference component applied to the second beam by the first beam; and adding the generated cancellation signal to a transmission signal output to the second subarray.
    Type: Application
    Filed: September 13, 2021
    Publication date: June 9, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Tomoya Ota, HIROYOSHI ISHIKAWA, TORU MANIWA
  • Publication number: 20220165328
    Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 26, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Toru Ishikawa, Takuya Nakanishi, Shinji Bessho
  • Patent number: 11340984
    Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Nakanishi, Toru Ishikawa, Minari Arai
  • Publication number: 20220157796
    Abstract: A composite integrated film includes a base member thin film having a base member first surface and a base member second surface facing each other, one or more penetration parts penetrating the base member first surface and the base member second surface of the base member thin film, one or more electrodes each including an electrical path part formed between the base member first surface and the base member second surface via the penetration part and an electrode surface in a planar shape formed on the base member second surface's side, and one or more elements provided on the base member first surface of the base member thin film and electrically connected to the electrodes, wherein the electrode surface and the base member second surface form a same flat surface.
    Type: Application
    Filed: October 18, 2021
    Publication date: May 19, 2022
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Takuma ISHIKAWA, Takahito SUZUKI, Kenichi TANIGAWA, Hironori FURUTA, Toru KOSAKA, Yusuke NAKAI, Shinya JYUMONJI, Genichiro MATSUO, Chihiro TAKAHASHI, Hiroto KAWADA, Yuuki SHINOHARA
  • Patent number: 11315620
    Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Takuya Nakanishi, Shinji Bessho
  • Patent number: 11290103
    Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods is disclosed. An apparatus includes a pull-up SCRC transistor, a pull-down SCRC transistor, and a charge transfer circuit. The pull-up SCRC transistor includes a pull-up gate terminal. The pull-down SCRC transistor includes a pull-down gate terminal. The charge transfer circuit is electrically connected between the pull-up gate terminal and the pull-down gate terminal. The charge transfer circuit is configured to transfer charge between the pull-up gate terminal and the pull-down gate terminal.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Yuan He, Toru Ishikawa
  • Patent number: 11270750
    Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Takuya Nakanishi, Shinji Bessho
  • Publication number: 20220066875
    Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
    Type: Application
    Filed: October 13, 2021
    Publication date: March 3, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Toru Ishikawa, Minari Arai
  • Patent number: 11238915
    Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Takuya Nakanishi, Shinji Bessho
  • Publication number: 20220020422
    Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Toru Ishikawa, Minari Arai, Nobuki Takahashi
  • Patent number: 11217325
    Abstract: In some examples, a memory device may include an internal synchronization circuit that provides for double data rate operation of the memory device when external single data rate signals are provided to the memory device. The external signals may be command and/or address signals provided by an external testing circuits in some examples. The internal synchronization circuit may latch and/or delay at least some of the external signals such that different external commands are provided at the rising and falling edges of the clock signal of the memory device. The memory device may latch the external signals at both the rising and falling edges of the clock signal for double data rate operation of the memory device.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan Hsuan Jhang, Toru Ishikawa, Takuya Nakanishi
  • Publication number: 20210406123
    Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Takuya Nakanishi, Toru Ishikawa, Minari Arai
  • Patent number: 11183260
    Abstract: Memory devices are disclosed. A memory device may include a number of fuses and a number of transmit lines configured to transmit data from the number of fuses. The memory device may also include a number of monitoring circuits. Each monitoring circuit of the number of monitoring circuits is coupled to a transmit line of the number of transmit lines. Each monitoring circuit comprises logic configured to receive the data from the number fuses via the transmit line. The logic is further configured to generate a result responsive to the data and indicative of pass/fail status of the transmit line. Associated methods and systems are also disclosed.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: November 23, 2021
    Assignee: Micron Technology Inc.
    Inventors: Yoshinori Fujiwara, Dave Jefferson, Jason M. Johnson, Vivek Kotti, Minoru Someya, Toru Ishikawa, Kevin G. Werhane
  • Patent number: 11169876
    Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Minari Arai
  • Publication number: 20210202004
    Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.
    Type: Application
    Filed: February 25, 2021
    Publication date: July 1, 2021
    Inventors: Toru Ishikawa, Minari Arai
  • Publication number: 20210200630
    Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 1, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Toru Ishikawa, Minari Arai
  • Patent number: 11037616
    Abstract: A system for refresh operations in semiconductor memories, and an apparatus and method therefore, are described. The system includes, for example, memory cells in memory banks that are refreshed during a self-refresh operation or an auto refresh operation. The self-refresh operation includes a different number of refresh activations than the auto refresh operation. The system further includes a row control circuit configured to refresh the memory cells in the memory banks based on refresh control signals received from a refresh control circuit, the refresh control signals provided by the refresh control circuit based on internal control signals received by the refresh control circuit from a command control circuit. The auto refresh operation includes a per bank refresh operation configured to refresh a corresponding memory bank or an all-bank refresh operation configured to refresh all memory banks.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Shinji Bessho, Takuya Nakanishi
  • Patent number: 11038395
    Abstract: A winding-start receiving groove in which a winding-start lead wire of a field coil is received is formed in an inner surface of a flange of an insulation bobbin. A holder is disposed on the flange and located on a radially outer side of the winding-start receiving groove. The holder is formed with a holder groove located on an extension line of the winding-start receiving groove and extending at an angle relative to a radial direction of the insulation bobbin. The winding-start lead wire of the field coil is received in the winding-start receiving groove and the holder groove and held by the holder. This makes it possible to obtain a rotor of a rotary electrical machine with a simplified configuration at low cost not only to improve winding workability but also to enhance electrical reliability and durability.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: June 15, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shintaro Shimizu, Kenji Maekawa, Toru Ishikawa, Yoshiro Imazawa
  • Patent number: 11011218
    Abstract: A system for refresh operations including multiple refresh activations, and a method and an apparatus therefore, are described. The system includes, for example, a memory array; a command address input circuit configured to provide a command for a per bank refresh operation or an all-bank refresh operation, a command control circuit configured to receive the command, and provide first and second internal control signals; a refresh control circuit configured to provide a first refresh control signal; and a row control circuit configured to provide a second refresh control signal. The provided first internal control signal is based on the provided command. For the per bank refresh operation, the provided second internal control signal is based on the second refresh control signal, and, for the all-bank refresh operation, the provided second internal control signal is based on the first internal control signal delayed by the command control circuit.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shinji Bessho, Toru Ishikawa, Takuya Nakanishi
  • Patent number: 10984868
    Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Minari Arai