Patents by Inventor Toru Mitsuki

Toru Mitsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8384084
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Publication number: 20120171795
    Abstract: A method of performing irradiation of laser light is given as a method of crystallizing a semiconductor film. However, if laser light is irradiated to a semiconductor film, the semiconductor film is instantaneously melted and expands locally. The temperature gradient between a substrate and the semiconductor film is precipitous, distortions may develop in the semiconductor film. Thus, the film quality of the crystalline semiconductor film obtained will drop in some cases. With the present invention, distortions of the semiconductor film are reduced by heating the semiconductor film using a heat treatment process after performing crystallization of the semiconductor film using laser light. Compared to the localized heating due to the irradiation of laser light, the heat treatment process is performed over the entire substrate and semiconductor film. Therefore, it is possible to reduce distortions formed in the semiconductor film and to increase the physical properties of the semiconductor film.
    Type: Application
    Filed: March 15, 2012
    Publication date: July 5, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Toru Mitsuki, Tamae Takano
  • Patent number: 7928438
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: April 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Publication number: 20100295046
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Application
    Filed: August 4, 2010
    Publication date: November 25, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hisashi OHTANI, Toru MITSUKI, Akiharu MIYANAGA, Yasushi OGATA
  • Patent number: 7772592
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: August 10, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Patent number: 7618904
    Abstract: When a laser beam is irradiated onto a semiconductor film, a steep temperature gradient is produced between a substrate and the semiconductor film. For this reason, the semiconductor film contracts, so that a warp in the film occurs. Therefore, the quality of a resulting crystalline semiconductor film sometimes deteriorates. According to the present invention, it is characterized in that, after laser beam crystallization on the semiconductor film, heat treatment is carried out so as to reduce the warp in the film. Since the substrate contracts by the heat treatment, the warp in the semiconductor film is lessened, so that the physical properties of the semiconductor film can be improved.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: November 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Tamae Takano
  • Patent number: 7573110
    Abstract: Method of fabricating TFTs (thin-film transistors) having a crystallized silicon film and a gate-insulating film. First, an amorphous silicon film is formed on an insulating substrate. A first dielectric film is formed from silicon oxide on the amorphous silicon film. Holes are formed in the first dielectric film to selectively expose the surface of the amorphous silicon film. Nickel is introduced as the metal element into the amorphous silicon film. The film is heat-treated, thus forming crystallized silicon film. This crystalline silicon film is etched together with the silicon oxide film to form an active layer. The etched silicon oxide film acts as the aforementioned gate-insulating film. Even after the crystallization step, the silicon oxide film is left behind. As a result, the interface with the crystalline silicon film is kept in a good state.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: August 11, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Toru Mitsuki
  • Patent number: 7538011
    Abstract: An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing a noble (rare) gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: May 26, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osama Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
  • Patent number: 7503975
    Abstract: In a crystalline silicon film fabricated by a related art method, the orientation planes of its crystal randomly exist and the orientation rate relative to a particular crystal orientation is low. A semiconductor material which contains silicon as its main component and 0.1-10 atomic % of germanium is used as a first layer, and an amorphous silicon film is used as a second layer. Laser light is irradiated to crystallize the amorphous semiconductor films, whereby a good semiconductor film is obtained. In addition, TFTs are fabricated by using such a semiconductor film.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: March 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
  • Patent number: 7485553
    Abstract: A first amorphous semiconductor film is formed on an insulating surface. A catalyst element for promoting crystallization is added thereto. Thereafter, by a first heat treatment in an inert gas, a first crystalline semiconductor film is formed. A barrier layer and a second semiconductor layer are formed on the first crystalline semiconductor film. The second semiconductor layer contains a rare gas element at a concentration of 1×1019 to 2×1022/cm3, preferably 1×1020 to 1×1021/cm3 and oxygen at a concentration of 5×1017 to 1×1021/cm3. Subsequently, by a second treatment in an inert gas, the catalyst element remaining in the first crystalline semiconductor film is moved to the second semiconductor film.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: February 3, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Hideto Ohnuma, Tamae Takano, Kenji Kasahara, Koji Dairiki
  • Patent number: 7459354
    Abstract: The crystallization method by laser light irradiation forms a multiplicity of convexes (ridges) in the surface of an obtained crystalline semiconductor film, deteriorating film quality. Therefore, it is a problem to provide a method for forming a ridge-reduced semiconductor film and a semiconductor device using such a semiconductor film. The present invention is characterized by heating a semiconductor film due to a heat processing method (RTA method: Rapid Thermal Anneal method) to irradiate light emitted from a lamp light source after crystallizing the semiconductor film by laser light, thereby reducing the ridge.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: December 2, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Toru Mitsuki
  • Patent number: 7368335
    Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 6, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki, Takeshi Shichi
  • Publication number: 20080087894
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Application
    Filed: November 19, 2007
    Publication date: April 17, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Patent number: 7326604
    Abstract: In a semiconductor device using a crystalline semiconductor film on a substrate 106 having an insulating surface, impurities are locally implanted into an active region 102 to form a pinning region 104. The pinning region 104 suppresses the spread of a depletion layer from the drain side to effectively prevent the short channel effect. Also, since a channel forming region 105 is intrinsic or substantially intrinsic, a high mobility is realized.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: February 5, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Toru Mitsuki, Takeshi Fukunaga
  • Patent number: 7316947
    Abstract: An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing a noble (rare) gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: January 8, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
  • Publication number: 20070298555
    Abstract: An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing an inert gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.
    Type: Application
    Filed: August 7, 2007
    Publication date: December 27, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
  • Patent number: 7307282
    Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: December 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
  • Patent number: 7307007
    Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 ?m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: December 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 7306982
    Abstract: It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (105), a second semiconductor film (106), and a third semiconductor layer (108) containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film (104) having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film (104) is allowed to pass through the barrier layer (105) and the second semiconductor film (106) by a heat treatment to move into the third semiconductor film (107). Afterward, the second and third semiconductor films (106) and (107) are removed with the barrier layer (105) used as an etching stopper.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: December 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
  • Patent number: 7297978
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: November 20, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata