Patents by Inventor Toru Mitsuki

Toru Mitsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020038889
    Abstract: The orientation of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is improved and a TFT formed from this crystalline semiconductor film is provided. In a semiconductor device whose TFT is formed from a semiconductor layer mainly containing silicon, the semiconductor layer has a channel formation region and an impurity region doped with an impurity of one type of conductivity.
    Type: Application
    Filed: June 18, 2001
    Publication date: April 4, 2002
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
  • Publication number: 20020014625
    Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.
    Type: Application
    Filed: August 1, 2001
    Publication date: February 7, 2002
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki
  • Publication number: 20020013022
    Abstract: Contamination of an interface of respective films constituting a TFT due to an contaminant impurity in a clean room atmosphere becomes a great factor to lower the reliability of the TFT. Besides, when an impurity is added to a crystalline semiconductor film, its crystal structure is broken. By using an apparatus for manufacturing a semiconductor device including a plurality of treatment chambers, a treatment can be made without being exposed to a clean room atmosphere in an interval between respective treatment steps, and it becomes possible to keep the interface of the respective films constituting the TFT clean. Besides, by carrying out crystallization after an impurity is added to an amorphous semiconductor film, the breakdown of the crystal structure of the crystalline semiconductor film is prevented.
    Type: Application
    Filed: May 9, 2001
    Publication date: January 31, 2002
    Inventors: Shunpei Yamazaki, Taketomi Asami, Mitsuhiro Ichijo, Toru Mitsuki, Yoko Kanakubo
  • Publication number: 20020008286
    Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.
    Type: Application
    Filed: June 6, 2001
    Publication date: January 24, 2002
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
  • Patent number: 6337235
    Abstract: The object of the present invention is to develop a manufacturing process for fabricating thin film transistors by using a crystalline semiconductor film appropriately for the purpose, in which the crystalline semiconductor film is formed by using a catalyst which enables crystallization at a low temperature and is easily gettered. Low temperature crystallization is realized by introducing Cu, a catalyst, on the amorphous semiconductor film and performing a heat treatment. Cu is gettered by immersing the polycrystalline semiconductor film which slightly includes Cu into a chemical fluid selected from a group consisting of a chemical including oxygen namely sulfuric acid.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: January 8, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Toru Mitsuki
  • Patent number: 6326249
    Abstract: A semiconductor device comprising a substrate having an insulating surface layer and an active layer comprising a semiconductor thin film formed thereon, wherein the substrate and the insulating surface layer in contact with the substrate each has at least one concave part, and the influence of the concave part is removed by conducting a flattening treatment and heat treatment of the undercoat film of the semiconductor thin film.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: December 4, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 6294815
    Abstract: A semiconductor device comprising a substrate having an insulating surface layer and an active layer comprising a semiconductor thin film formed thereon, wherein the substrate and the insulating surface layer in contact with the substrate each has at least one concave part, and the influence of the concave part is removed by conducting a flattening treatment and heat treatment of the undercoat film of the semiconductor thin film.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: September 25, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 6107639
    Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 .mu.m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: August 22, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 6087679
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: July 11, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Patent number: 5966596
    Abstract: Method of fabricating TFTs (thin-film transistors) having a crystallized silicon film and a gate-insulating film. First, an amorphous silicon film is formed on an insulating substrate. A first dielectric film is formed from silicon oxide on the amorphous silicon film. Holes are formed in the first dielectric film to selectively expose the surface of the amorphous silicon film. Nickel is introduced as the metal element into the amorphous silicon film. The film is heat-treated, thus forming crystallized silicon film. This crystalline silicon film is etched together with the silicon oxide film to form an active layer. The etched silicon oxide film acts as the aforementioned gate-insulating film. Even after the crystallization step, the silicon oxide film is left behind. As a result, the interface with the crystalline silicon film is kept in a good state.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: October 12, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Toru Mitsuki