Patents by Inventor Toru Mitsuki

Toru Mitsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030162334
    Abstract: Contamination of an interface of respective films constituting a TFT due to an contaminant impurity in a clean room atmosphere becomes a great factor to lower the reliability of the TFT. Besides, when an impurity is added to a crystalline semiconductor film, its crystal structure is broken. By using an apparatus for manufacturing a semiconductor device including a plurality of treatment chambers, a treatment can be made without being exposed to a clean room atmosphere in an interval between respective treatment steps, and it becomes possible to keep the interface of the respective films constituting the TFT clean. Besides, by carrying out crystallization after an impurity is added to an amorphous semiconductor film, the breakdown of the crystal structure of the crystalline semiconductor film is prevented.
    Type: Application
    Filed: December 20, 2002
    Publication date: August 28, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Taketomi Asami, Mitsuhiro Ichijo, Toru Mitsuki, Yoko Kanakubo
  • Publication number: 20030102480
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Application
    Filed: November 18, 2002
    Publication date: June 5, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Publication number: 20030062522
    Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 3, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 6515299
    Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: February 4, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Publication number: 20030010980
    Abstract: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater.
    Type: Application
    Filed: July 9, 2002
    Publication date: January 16, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara
  • Patent number: 6506636
    Abstract: Contamination of an interface of respective films constituting a TFT due to an contaminant impurity in a clean room atmosphere becomes a great factor to lower the reliability of the TFT. Besides, when an impurity is added to a crystalline semiconductor film, its crystal structure is broken. By using an apparatus for manufacturing a semiconductor device including a plurality of treatment chambers, a treatment can be made without being exposed to a clean room atmosphere in an interval between respective treatment steps, and it becomes possible to keep the interface of the respective films constituting the TFT clean. Besides, by carrying out crystallization after an impurity is added to an amorphous semiconductor film, the breakdown of the crystal structure of the crystalline semiconductor film is prevented.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: January 14, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Taketomi Asami, Mitsuhiro Ichijo, Toru Mitsuki, Yoko Kanakubo
  • Publication number: 20020197785
    Abstract: A first amorphous semiconductor film is formed on an insulating surface. A catalyst element for promoting crystallization is added thereto. Thereafter, by a first heat treatment in an inert gas, a first crystalline semiconductor film is formed. A barrier layer and a second semiconductor layer are formed on the first crystalline semiconductor film. The second semiconductor layer contains a rare gas element at a concentration of 1×1019 to 2×1022/cm3, preferably 1×1020 to 1×1021/cm3 and oxygen at a concentration of 5×1017 to 1×1021/cm3. Subsequently, by a second treatment in an inert gas, the catalyst element remaining in the first crystalline semiconductor film is moved to the second semiconductor film.
    Type: Application
    Filed: March 15, 2002
    Publication date: December 26, 2002
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO. LTD.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Hideto Ohnuma, Tamae Takano, Kenji Kasahara, Koji Dairiki
  • Patent number: 6495886
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: December 17, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Publication number: 20020164843
    Abstract: A technique of using a metal element that has a catalytic action over crystallization of a semiconductor film to obtain a crystalline semiconductor film and then effectively removing the metal element remaining in the film is provided. A first semiconductor film (104) having a crystal structure is formed on a substrate. A barrier layer (105) and a second semiconductor film (106) containing a rare gas element are formed on the first semiconductor film (104). A metal element contained in the first semiconductor film (104) is moved to the second semiconductor film (106) through the barrier layer (105) by heat treatment for gettering.
    Type: Application
    Filed: March 15, 2002
    Publication date: November 7, 2002
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Koji Dairiki, Toru Mitsuki, Toru Takayama, Kengo Akimoto
  • Publication number: 20020155652
    Abstract: An orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is increased, a distortion thereof is suppressed, and a TFT using such a crystalline semiconductor film is provided. At the time of formation of the amorphous semiconductor film (102) or after the formation thereof a noble gas element, typically, argon is included in the film and crystallization is performed therefor. Thus, an orientation ratio of the semiconductor film (104) can be increased and a distortion present in the semiconductor film (104) after the crystallization is suppressed as compared with that present in the semiconductor film before the crystallization. Then, the noble gas element in the film is removed or reduced by laser light irradiation performed later.
    Type: Application
    Filed: March 25, 2002
    Publication date: October 24, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki
  • Publication number: 20020155706
    Abstract: The number of grains in active regions of devices can be made uniform by making the grains of crystalline semiconductor films, obtained by thermal crystallization using a metal element, smaller. The present invention is characterized in that a semiconductor film is exposed within an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma, and then thermal crystallization using a metal element is performed. The concentration of crystal nuclei1 generated is thus increased, making the grain size smaller, by performing these processes. Heat treatment may also be performed, of course, after exposing the semiconductor film, to which the metal element is added, to an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma.
    Type: Application
    Filed: March 6, 2002
    Publication date: October 24, 2002
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO. LTD.
    Inventors: Toru Mitsuki, Takeshi Shichi, Shinji Maekawa, Hiroshi Shibata, Akiharu Miyanaga
  • Publication number: 20020151120
    Abstract: An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing an inert gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.
    Type: Application
    Filed: February 12, 2002
    Publication date: October 17, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
  • Publication number: 20020127827
    Abstract: A method of performing irradiation of laser light is given as a method of crystallizing a semiconductor film. However, if laser light is irradiated to a semiconductor film, the semiconductor film is instantaneously melted and expands locally. The temperature gradient between a substrate and the semiconductor film is precipitous, distortions may develop in the semiconductor film. Thus, the film quality of the crystalline semiconductor film obtained will drop in some cases. With the present invention, distortions of the semiconductor film are reduced by heating the semiconductor film using a heat treatment process after performing crystallization of the semiconductor film using laser light. Compared to the localized heating due to the irradiation of laser light, the heat treatment process is performed over the entire substrate and semiconductor film. Therefore, it is possible to reduce distortions formed in the semiconductor film and to increase the physical properties of the semiconductor film.
    Type: Application
    Filed: February 20, 2002
    Publication date: September 12, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Tamae Takano
  • Publication number: 20020119633
    Abstract: When a laser beam is irradiated onto a semiconductor film, a steep temperature gradient is produced between a substrate and the semiconductor film. For this reason, the semiconductor film contracts, so that a warp in the film occurs. Therefore, the quality of a resulting crystalline semiconductor film sometimes deteriorates. According to the present invention, it is characterized in that, after laser beam crystallization on the semiconductor film, heat treatment is carried out so as to reduce the warp in the film. Since the substrate contracts by the heat treatment, the warp in the semiconductor film is lessened, so that the physical properties of the semiconductor film can be improved.
    Type: Application
    Filed: February 25, 2002
    Publication date: August 29, 2002
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shumpei Yamazaki, Toru Mitsuki, Tamae Takano
  • Publication number: 20020119585
    Abstract: The crystallization method by laser light irradiation forms a multiplicity of convexes (ridges) in the surface of an obtained crystalline semiconductor film, deteriorating film quality. Therefore, it is a problem to provide a method for forming a ridge-reduced semiconductor film and a semiconductor device using such a semiconductor film. The present invention is characterized by heating a semiconductor film due to a heat processing method (RTA method: Rapid Thermal Anneal method) to irradiate light emitted from a lamp light source after crystallizing the semiconductor film by laser light, thereby reducing the ridge.
    Type: Application
    Filed: January 28, 2002
    Publication date: August 29, 2002
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Toru Mitsuki
  • Publication number: 20020115271
    Abstract: It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (105), a second semiconductor film (106), and a third semiconductor layer (108) containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film (104) having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film (104) is allowed to pass through the barrier layer (105) and the second semiconductor film (106) by a heat treatment to move into the third semiconductor film (107). Afterward, the second and third semiconductor films (106) and (107) are removed with the barrier layer (105) used as an etching stopper.
    Type: Application
    Filed: February 14, 2002
    Publication date: August 22, 2002
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
  • Patent number: 6388270
    Abstract: To provide a semiconductor device utilizing a semiconductor film having a high crystallinity by a production process having a high mass productivity. Upon crystallizing an amorphous silicon film 106, germanium is used as a catalyst element for accelerating the crystallization. A heat treatment is conducted in a condition in that a germanium film 107 is formed on the amorphous silicon film 106, and thus a polysilicon film 108 is obtained by the catalytic function of germanium. The polysilicon film 108 thus obtained has crystallinity that can be substantially regarded as a single crystal.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: May 14, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki
  • Publication number: 20020043660
    Abstract: In a crystalline silicon film fabricated by a related art method, the orientation planes of its crystal randomly exist and the orientation rate relative to a particular crystal orientation is low. A semiconductor material which contains silicon as its main component and 0.1-10 atomic % of germanium is used as a first layer, and an amorphous silicon film is used as a second layer. Laser light is irradiated to crystallize the amorphous semiconductor films, whereby a good semiconductor film is obtained. In addition, TFTs are fabricated by using such a semiconductor film.
    Type: Application
    Filed: June 25, 2001
    Publication date: April 18, 2002
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
  • Publication number: 20020043662
    Abstract: Crystal orientation planes exist randomly in a crystalline silicon film manufactured by a conventional method, and the orientation ratio is low with respect to a specific crystal orientation. A semiconductor film having a high orientation ratio for the {101} lattice plane is obtained if crystallization of an amorphous semiconductor film, which has silicon as its main constituent and contains from 0.1 to 10 atom % germanium, is performed after introduction of a metal element. A TFT is manufactured utilizing the semiconductor film.
    Type: Application
    Filed: June 14, 2001
    Publication date: April 18, 2002
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kashahara, Taketomi Asami, Tamae Takano, Takeshi Shinichi, Chiho Kokubo
  • Publication number: 20020042170
    Abstract: A semiconductor device comprising a substrate having an insulating surface layer and an active layer comprising a semiconductor thin film formed thereon, wherein the substrate and the insulating surface layer in contact with the substrate each has at least one concave part, and the influence of the concave part is removed by conducting a flattening treatment and heat treatment of the undercoat film of the semiconductor thin film.
    Type: Application
    Filed: September 19, 2001
    Publication date: April 11, 2002
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani