Patents by Inventor Toru Mitsuki
Toru Mitsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040259389Abstract: The crystallization method by laser light irradiation forms a multiplicity of convexes (ridges) in the surface of an obtained crystalline semiconductor film, deteriorating film quality. Therefore, it is a problem to provide a method for forming a ridge-reduced semiconductor film and a semiconductor device using such a semiconductor film. The present invention is characterized by heating a semiconductor film due to a heat processing method (RTA method: Rapid Thermal Anneal method) to irradiate light emitted from a lamp light source after crystallizing the semiconductor film by laser light, thereby reducing the ridge.Type: ApplicationFiled: July 23, 2004Publication date: December 23, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Toru Mitsuki
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Patent number: 6830994Abstract: The number of grains in active regions of devices can be made uniform by making the grains of crystalline semiconductor films, obtained by thermal crystallization using a metal element, smaller. The present invention is characterized in that a semiconductor film is exposed within an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma, and then thermal crystallization using a metal element is performed. The concentration of crystal nuclei1 generated is thus increased, making the grain size smaller, by performing these processes. Heat treatment may also be performed, of course, after exposing the semiconductor film, to which the metal element is added, to an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma.Type: GrantFiled: March 6, 2002Date of Patent: December 14, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Mitsuki, Takeshi Shichi, Shinji Maekawa, Hiroshi Shibata, Akiharu Miyanaga
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Patent number: 6828587Abstract: Crystal orientation planes exist randomly in a crystalline silicon film manufactured by a conventional method, and the orientation ratio is low with respect to a specific crystal orientation. A semiconductor film having a high orientation ratio for the {101} lattice plane is obtained if crystallization of an amorphous semiconductor film, which has silicon as its main constituent and contains from 0.1 to 10 atom % germanium, is performed after introduction of a metal element. A TFT is manufactured utilizing the semiconductor film.Type: GrantFiled: June 14, 2001Date of Patent: December 7, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
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Patent number: 6828179Abstract: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater.Type: GrantFiled: July 9, 2002Date of Patent: December 7, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara
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Patent number: 6822262Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.Type: GrantFiled: November 18, 2002Date of Patent: November 23, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
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Patent number: 6812081Abstract: An orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is increased, a distortion thereof is suppressed, and a TFT using such a crystalline semiconductor film is provided. At the time of formation of the amorphous semiconductor film (102) or after the formation thereof a noble gas element, typically, argon is included in the film and crystallization is performed therefor. Thus, an orientation ratio of the semiconductor film (104) can be increased and a distortion present in the semiconductor film (104) after the crystallization is suppressed as compared with that present in the semiconductor film before the crystallization. Then, the noble gas element in the film is removed or reduced by laser light irradiation performed later.Type: GrantFiled: March 25, 2002Date of Patent: November 2, 2004Assignee: Semiconductor Energy Laboratory Co.,.Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki
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Patent number: 6808968Abstract: It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (105), a second semiconductor film (106), and a third semiconductor layer (108) containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film (104) having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film (104) is allowed to pass through the barrier layer (105) and the second semiconductor film (106) by a heat treatment to move into the third semiconductor film (107). Afterward, the second and third semiconductor films (106) and (107) are removed with the barrier layer (105) used as an etching stopper.Type: GrantFiled: February 14, 2002Date of Patent: October 26, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
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Publication number: 20040201023Abstract: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby. providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater.Type: ApplicationFiled: April 30, 2004Publication date: October 14, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara
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Publication number: 20040201022Abstract: The orientation of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is improved and a TFT formed from this crystalline semiconductor film is provided. In a semiconductor device whose TFT is formed from a semiconductor layer mainly containing silicon, the semiconductor layer has a channel formation region and an impurity region doped with an impurity of one type of conductivity.Type: ApplicationFiled: April 29, 2004Publication date: October 14, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
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Publication number: 20040183132Abstract: In a semiconductor device using a crystalline semiconductor film on a substrate 106 having an insulating surface, impurities are locally implanted into an active region 102 to form a pinning region 104. The pinning region 104 suppresses the spread of a depletion layer from the drain side to effectively prevent the short channel effect. Also, since a channel forming region 105 is intrinsic or substantially intrinsic, a high mobility is realized.Type: ApplicationFiled: January 29, 2004Publication date: September 23, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japan corporationInventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Toru Mitsuki, Takeshi Fukunaga
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Patent number: 6787807Abstract: The orientation of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is improved and a TFT formed from this crystalline semiconductor film is provided. In a semiconductor device whose TFT is formed from a semiconductor layer mainly containing silicon, the semiconductor layer has a channel formation region and an impurity region doped with an impurity of one type of conductivity.Type: GrantFiled: June 18, 2001Date of Patent: September 7, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
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Publication number: 20040169177Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.Type: ApplicationFiled: March 4, 2004Publication date: September 2, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japan corporationInventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki, Takeshi Shichi
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Patent number: 6770518Abstract: The crystallization method by laser light irradiation forms a multiplicity of convexes (ridges) in the surface of an obtained crystalline semiconductor film, deteriorating film quality. Therefore, it is a problem to provide a method for forming a ridge-reduced semiconductor film and a semiconductor device using such a semiconductor film. The present invention is characterized by heating a semiconductor film due to a heat processing method (RTA method: Rapid Thermal Anneal method) to irradiate light emitted from a lamp light source after crystallizing the semiconductor film by laser light, thereby reducing the ridge.Type: GrantFiled: January 28, 2002Date of Patent: August 3, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Toru Mitsuki
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Publication number: 20040132233Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.Type: ApplicationFiled: December 19, 2003Publication date: July 8, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
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Publication number: 20040108576Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.Type: ApplicationFiled: December 5, 2003Publication date: June 10, 2004Applicant: Semiconductor Energy Laboratory, Co., Ltd., a Japan corporationInventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
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Patent number: 6720575Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.Type: GrantFiled: October 4, 2002Date of Patent: April 13, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
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Patent number: 6703265Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.Type: GrantFiled: August 1, 2001Date of Patent: March 9, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki, Takeshi Shichi
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Patent number: 6693299Abstract: In a semiconductor device using a crystalline semiconductor film on a substrate 106 having an insulating surface, impurities are locally implanted into an active region 102 to form a pinning region 104. The pinning region 104 suppresses the spread of a depletion layer from the drain side to effectively prevent the short-channel effect. Also, since a channel forming region 105 is intrinsic or substantially intrinsic, a high mobility is realized.Type: GrantFiled: July 13, 1998Date of Patent: February 17, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Toru Mitsuki, Takeshi Fukunaga
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Patent number: 6690068Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.Type: GrantFiled: June 6, 2001Date of Patent: February 10, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
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Patent number: 6635929Abstract: A semiconductor device comprising a substrate having an insulating surface layer and an active layer comprising a semiconductor thin film formed thereon, wherein the substrate and the insulating surface layer in contact with the substrate each has at least one concave part, and the influence of the concave part is removed by conducting a flattening treatment and heat treatment of the undercoat film of the semiconductor thin film.Type: GrantFiled: September 19, 2001Date of Patent: October 21, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani