Patents by Inventor Toru Miwa

Toru Miwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081192
    Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 3, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Publication number: 20210233589
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Ken Oowada, Toru Miwa
  • Publication number: 20210142858
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Publication number: 20210134828
    Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
  • Publication number: 20210134375
    Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10984874
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Patent number: 10978156
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 13, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Ken Oowada, Toru Miwa
  • Patent number: 10885984
    Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10854619
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Patent number: 10734080
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Publication number: 20200185397
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Publication number: 20200185039
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Patent number: 10635526
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Yibo Yin, Henry Zhang, Po-Shen Lai, Vijay Chinchole, Spyridon Georgakis, Yan Li, Hiroyuki Mizukoshi, Toru Miwa, Jayesh Pakhale, Tz-Yi Liu
  • Publication number: 20200005871
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang YANG, Aaron LEE, Gerrit Jan HEMINK, Ken OOWADA, Toru MIWA
  • Publication number: 20180357123
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.
    Type: Application
    Filed: March 23, 2018
    Publication date: December 13, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Yibo Yin, Henry Zhang, Po-Shen Lai, Vijay Chinchole, Spyridon Georgakis, Yan Li, Hiroyuki Mizukoshi, Toru Miwa, Jayesh Pakhale, Tz-Yi Liu
  • Patent number: 9941297
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Publication number: 20170263642
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Application
    Filed: May 30, 2017
    Publication date: September 14, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Patent number: 9691781
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 27, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Publication number: 20170162592
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 8, 2017
    Applicant: SanDisk Technologies Inc.
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Patent number: 9646981
    Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 9, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Ryoichi Honma, Toru Miwa, Masahide Matsumoto, Yuki Mizutani, Hiroaki Koketsu