Patents by Inventor Toru Tatsumi

Toru Tatsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5691249
    Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: November 25, 1997
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Toru Tatsumi
  • Patent number: 5623243
    Abstract: A semiconductor device having a roughed surface, which is useful for a capacitor electrode is disclosed. The device is featured by depositing a polycrystalline silicon layer in such a manner that polycrystalline grains having a hemispherical like shape or a mushroom like shape are caused at the surface of the polycrystalline silicon layer. A dielectric is formed on the polycrystalline layer having an uneven surface. A conductive layer is formed on the dielectric layer. The semiconductor device thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area from the hemispherical like shaped or mushroom like shaped polycrystalline grains.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: April 22, 1997
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Toru Tatsumi
  • Patent number: 5571735
    Abstract: In a method of manufacturing a semiconductor device, a step (d) of forming metal silicide films (20) on source and drain regions (17, 18) and on gate electrodes (71, 81) comprises selectively depositing silicon thin films (19) on the source and drain regions and the gate electrodes, the silicon thin films having impurity concentration less than 10.sup.19 cm.sup.-3 ; amorphizing the silicon thin films, the gate electrodes, and a silicon semiconductor substrate (11) by ion implantation; depositing a metal film on the silicon thin films, on the gate electrodes, and on the silicon semiconductor substrate; performing heat treatment of the metal film to form the metal silicide films (20) on the source and drain regions and the gate electrodes; and removing unreacted metal films (21) remaining on insulating films (16-1, 16-2). Preferably, the selectively depositing step may be performed by a chemical vapor deposition process of a reaction rate-determining mode by using disilane gas or silane gas.
    Type: Grant
    Filed: June 16, 1995
    Date of Patent: November 5, 1996
    Assignee: NEC Corporation
    Inventors: Tohru Mogami, Toru Tatsumi
  • Patent number: 5441012
    Abstract: A thin film deposition method consists of placing a wafer or substrate whose surface contains at least two kinds of materials inside a vacuum chamber or vessel, supplying a reactant gas into the vacuum chamber or vessel, the reactant gas containing molecules having a low sticking coefficient relative to at least one of the at least two kinds of materials, and allowing an epitaxial growth to occur on the other kinds of materials contained in the wafer or substrate.The method further includes setting the pressure inside the vacuum chamber or vessel filled with the reactant gas equal to a pressure range in which the mean free path (d) of the reactant gas molecules is longer than the shortest distance (L) between the wafer or substrate placed inside the vacuum chamber or vessel and the vacuum side-exposed wall of the vacuum chamber or vessel, i.e., d>L.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: August 15, 1995
    Assignees: ANELVA Corporation, NEC Corporation
    Inventors: Ken-ichi Aketagawa, Junro Sakai, Toru Tatsumi
  • Patent number: 5385863
    Abstract: A method of fabricating a polysilicon film whose crystal grain size can be controlled in a wide range and which has a large surface area and an application thereof to a DRAM are disclosed. In polycrystallizing an amorphous silicon film having a substantially clean surface, nucleation and crystal growth are performed under different conditions. With this method, crystal grain density and crystal grain size can be controlled easily, causing a polysilicon film having finer grains to be formed concomitant with reduction of capacitor area due to increase of integration density of DRAM.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: January 31, 1995
    Assignee: NEC Corporation
    Inventors: Toru Tatsumi, Akira Sakai
  • Patent number: 5366917
    Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable fur a capacitor electrode because of its increased effective surface area.
    Type: Grant
    Filed: March 19, 1991
    Date of Patent: November 22, 1994
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Toru Tatsumi
  • Patent number: 5284521
    Abstract: A vacuum film forming apparatus including a vacuum vessel having an interior divided into a first vacuum chamber and a second vacuum chamber. First evacuating means is arranged for the first vacuum chamber while it is communicated with the first vacuum chamber, and second evacuating means is arranged for the second vacuum chamber while it is communicated with the second vacuum chamber. In addition, a substrate heater is arranged in the first vacuum chamber, and gas supplying means is arranged in the second vacuum chamber. The apparatus further includes a substrate holder for holding a substrate thereon such that a film forming surface of the substrate is oriented toward the second vacuum chamber. The substrate holder is arranged at a position where the first vacuum chamber and the second vacuum chamber are gastightly isolated from each other with the substrate holder interposed therebetween together with the substrate.
    Type: Grant
    Filed: September 4, 1991
    Date of Patent: February 8, 1994
    Assignees: Anelva Corporation, NEC Corporation
    Inventors: Ken-ichi Aketagawa, Junro Sakai, Shun-ichi Murakami, Hiroyoshi Murota, Toru Tatsumi
  • Patent number: 5234862
    Abstract: A thin film deposition method consists of depositing a thin film on a wafer by supplying a reactant gas molecules toward and onto the wafer within a vacuum vessel or chamber. The pressure within the vacuum vessel is set to the pressure under which the mean free path (d) of the molecules contained in the supplied reactant gas can be longer than the shortest distance (L) between the wafer and the wall of the vacuum vessel exposed to the vacuum side, or d>L. The temperature of the wafer is set to the temperature (T sub) at which the reactant gas can cause substantially the thermally decomposing reaction. The temperature of the vacuum side-exposed wall of the vacuum vessel (T wall) is set to a temperature range having the lower limit higher than the temperature (T vap) at which the saturated vapor pressure can be maintained to be equal to the partial pressure of the molecules contained in the reactant gas, and having the upper limit lower than the temperature of the wafer (T sub), or T vap<T wall<T sub.
    Type: Grant
    Filed: September 9, 1991
    Date of Patent: August 10, 1993
    Assignees: Anelva Corp., NEC Corp.
    Inventors: Ken-ichi Aketagawa, Junro Sakai, Toru Tatsumi, Shun-Ichi Murakami, Hiroyoshi Murota