Patents by Inventor Toshiaki Iwamatsu

Toshiaki Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050101070
    Abstract: An SOI substrate is formed of a silicon oxide substrate and a silicon film. A surface of the silicon film is oxidized and a silicon oxide film is thereby formed. A polycrystalline silicon and a silicon nitride film are formed on the silicon oxide film in this order. Then, a trench is formed in a region. The trench is filled with an insulating material, e.g., a silicon oxide film.
    Type: Application
    Filed: November 2, 2004
    Publication date: May 12, 2005
    Inventors: Mikio Tsujiuchi, Toshiaki Iwamatsu
  • Publication number: 20050101091
    Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
    Type: Application
    Filed: December 15, 2004
    Publication date: May 12, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto, Shigenobu Maeda
  • Patent number: 6879002
    Abstract: A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embedded between the active regions 3 in the silicon layer 3, wherein the insulating layer 2 has spaces 6 positioned in the vicinity of interfaces between the active regions and the element isolating parts 5, whereby it becomes possible to reduce fixed charges or holes existing on a side of the insulating layer in interfaces between the silicon layer and the insulating layer, which fixed charges or holes are generated in a process of oxidation for forming the insulating layer on a bottom surface of the silicon layer.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: April 12, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shoichi Miyamoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 6875663
    Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: April 5, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto, Shigenobu Maeda
  • Patent number: 6872979
    Abstract: A semiconductor substrate that prevents formation of particles from an edge part of the substrate. The substrate contains an on-substrate oxide film and an SOI layer stacked on the oxide film. A molten layer is formed on the edge part of the on-substrate oxide film and the SOI layer by mixing the SOI layer and the on-substrate oxide film to cover the edge part. An epitaxial layer may also be formed on the edge part of the on-substrate oxide film and the SOI layer to cover the edge part.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: March 29, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshiko Yoshida, Hideki Naruoka, Yasuhiro Kimura, Yasuo Yamaguchi, Toshiaki Iwamatsu, Yuuichi Hirano
  • Publication number: 20050037524
    Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
    Type: Application
    Filed: September 27, 2004
    Publication date: February 17, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Mikio Tsujiuchi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Shigeto Maegawa
  • Patent number: 6841400
    Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: January 11, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Mikio Tsujiuchi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Shigeto Maegawa
  • Publication number: 20040253458
    Abstract: A semiconductor wafer includes an oxide film above a silicon layer, and a porous silicon layer which is located above the oxide film and serves as a gettering layer. Gettering of impurities from a silicon layer is not interrupted by the oxide film since the porous silicon layer is placed above the oxide film. The semiconductor wafer having the structure above can be produced by a bonding method. Bonding strength relative to the oxide film is ensured by placing a growth silicon layer between the oxide film and the porous silicon layer, compared with the case in which the oxide film and the porous silicon layer are directly bonded.
    Type: Application
    Filed: July 14, 2004
    Publication date: December 16, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Takuji Matsumoto, Toshiaki Iwamatsu
  • Publication number: 20040227185
    Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.
    Type: Application
    Filed: January 12, 2004
    Publication date: November 18, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Takashi Ipposhi, Toshiaki Iwamatsu, Yuuichi Hirano
  • Patent number: 6818536
    Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: November 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu, Yasuo Yamaguchi
  • Publication number: 20040222465
    Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).
    Type: Application
    Filed: June 15, 2004
    Publication date: November 11, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Hirokazu Sayama, Shigenobu Maeda, Toshiaki Iwamatsu, Kazunobu Ota
  • Publication number: 20040207017
    Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.
    Type: Application
    Filed: May 10, 2004
    Publication date: October 21, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 6806537
    Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: October 19, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Hirokazu Sayama, Shigenobu Maeda, Toshiaki Iwamatsu, Kazunobu Ota
  • Patent number: 6798021
    Abstract: By ion implantation process, a P-type impurity for element isolation is implanted at an impurity concentration (P1) into a silicon layer (3) defined between the bottom surface of an element isolation insulating film (5a) and the upper surface of a BOX layer (2). Resulting from this implantation, a P-type impurity is implanted at an impurity concentration (P2) into the silicon layer (3) under a gate oxide film (7a) and in the vicinity of an interface between the silicon layer (3) and the BOX layer (2). Under a capacitor dielectric film (7b) and in the vicinity of an interface between the silicon layer (3) and the BOX layer (2), the silicon layer (3) has an impurity concentration (P0) which is the initial concentration of itself.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: September 28, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
  • Patent number: 6794717
    Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: September 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20040164353
    Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.
    Type: Application
    Filed: October 10, 2003
    Publication date: August 26, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Shigenobu Maeda, Shoichi Miyamoto, Akihiko Furukawa, Yasuo Inoue
  • Patent number: 6774435
    Abstract: A semiconductor wafer includes an oxide film above a silicon layer, and a porous silicon layer which is located above the oxide film and serves as a gettering layer. Gettering of impurities from a silicon layer is not interrupted by the oxide film since the porous silicon layer is placed above the oxide film. The semiconductor wafer having the structure above can be produced by a bonding method. Bonding strength relative to the oxide film is ensured by placing a growth silicon layer between the oxide film and the porous silicon layer, compared with the case in which the oxide film and the porous silicon layer are directly bonded.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: August 10, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Toshiaki Iwamatsu
  • Publication number: 20040150047
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 5, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20040135211
    Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 15, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
  • Publication number: 20040119133
    Abstract: A semiconductor device which enables an improvement of a current driving capability of a MOS transistor sufficiently is attained.
    Type: Application
    Filed: April 4, 2003
    Publication date: June 24, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Toshiaki Iwamatsu