Patents by Inventor Toshiaki Iwamatsu

Toshiaki Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060086934
    Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.
    Type: Application
    Filed: December 5, 2005
    Publication date: April 27, 2006
    Applicant: RENESAS TECHNOLOGY, INC.
    Inventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Shigenobu Maeda, Shoichi Miyamoto, Akihiko Furukawa, Yasuo Inoue
  • Publication number: 20060043494
    Abstract: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 2, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu, Shigeto Maegawa
  • Patent number: 7005705
    Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: February 28, 2006
    Assignee: Renesas Technology Corporation
    Inventors: Shigenobu Maeda, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 7001822
    Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: February 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Shigenobu Maeda, Shoichi Miyamoto, Akihiko Furukawa, Yasuo Inoue
  • Publication number: 20060017137
    Abstract: A semiconductor device and its manufacturing method are achieved which are capable of mixing a plurality of different crystal orientations in SOI substrate surfaces and controlling increase of leakage current into substrates and increase in power consumption in each area. An SOI substrate is fabricated by bonding two semiconductor wafers together so that the same <110> crystal orientations of those wafers are displaced at a predetermined angle (e.g., 45 degrees) with respect to each other. Part of the SOI substrate surface is then etched to a buried insulating layer, in which part epitaxial growth is conducted. Then, using the SIMOX technique, a buried oxide film is also formed in the area where an epitaxial growth layer is formed, so that the SOI structure is formed in each area.
    Type: Application
    Filed: July 21, 2005
    Publication date: January 26, 2006
    Applicant: Renesas Technology Corp.
    Inventor: Toshiaki Iwamatsu
  • Publication number: 20060006423
    Abstract: A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a <100> crystal direction notch (32a) and a <110> crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a <110> crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers.
    Type: Application
    Filed: September 13, 2005
    Publication date: January 12, 2006
    Applicant: Renesas Technology Corpo.
    Inventors: Toshiaki Iwamatsu, Shigenobu Maeda
  • Publication number: 20050275021
    Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.
    Type: Application
    Filed: August 5, 2005
    Publication date: December 15, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Takashi Ipposhi, Toshiaki Iwamatsu, Yuuichi Hirano
  • Publication number: 20050269637
    Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
    Type: Application
    Filed: May 26, 2005
    Publication date: December 8, 2005
    Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
  • Publication number: 20050253219
    Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.
    Type: Application
    Filed: June 21, 2005
    Publication date: November 17, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
  • Patent number: 6958266
    Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: October 25, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Patent number: 6953979
    Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: October 11, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Publication number: 20050212056
    Abstract: To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.
    Type: Application
    Filed: May 24, 2005
    Publication date: September 29, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Hideki Naruoka, Nobuyoshi Hattori, Shigeto Maegawa, Yasuo Yamaguchi, Takuji Matsumoto
  • Publication number: 20050208322
    Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.
    Type: Application
    Filed: February 24, 2005
    Publication date: September 22, 2005
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A.
    Inventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani
  • Publication number: 20050184342
    Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
    Type: Application
    Filed: April 19, 2005
    Publication date: August 25, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
  • Patent number: 6933565
    Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: August 23, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
  • Publication number: 20050167673
    Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
    Type: Application
    Filed: March 14, 2005
    Publication date: August 4, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
  • Publication number: 20050156242
    Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 21, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Patent number: 6914307
    Abstract: A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: July 5, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Hideki Naruoka, Nobuyoshi Hattori, Shigeto Maegawa, Yasuo Yamaguchi, Takuji Matsumoto
  • Publication number: 20050133864
    Abstract: Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. Each of the trench isolation films (4) includes a central portion which passes through the SOI layer (3) and reaches a buried oxide film (2) to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer (3) and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films (4) includes a hybrid-trench isolation structure.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 23, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 6902988
    Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising: a first sacrificial oxidation stage for removing material constituting the working layer (6) over a certain surface thickness of each substrate (1), a stage of polishing (200) the face which has been subjected to the first sacrificial oxidation stage (100), and a second sacrificial oxidation stage for again removing material constituting the working layer (6) on the polished face (17).
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: June 7, 2005
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani