Abstract: While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.

Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51< prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “?” functions as a gate electrode of an original MOS transistor.

Abstract: In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

Abstract: Formed on an insulator (9) are an N? type semiconductor layer (10) having a partial isolator formed on its surface and a P? type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.

Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A semiconductor device and its manufacturing method are achieved which are capable of mixing a plurality of different crystal orientations in SOI substrate surfaces and controlling increase of leakage current into substrates and increase in power consumption in each area. An SOI substrate is fabricated by bonding two semiconductor wafers together so that the same <110> crystal orientations of those wafers are displaced at a predetermined angle (e.g., 45 degrees) with respect to each other. Part of the SOI substrate surface is then etched to a buried insulating layer, in which part epitaxial growth is conducted. Then, using the SIMOX technique, a buried oxide film is also formed in the area where an epitaxial growth layer is formed, so that the SOI structure is formed in each area.

Abstract: A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a <100> crystal direction notch (32a) and a <110> crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a <110> crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers.

Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.