Patents by Inventor Toshiaki Iwamatsu

Toshiaki Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080274596
    Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.
    Type: Application
    Filed: June 2, 2008
    Publication date: November 6, 2008
    Applicant: Renesas Technology Corporation
    Inventors: Takuji MATSUMOTO, Toshiaki Iwamatsu, Yuuichi Hirano
  • Publication number: 20080261387
    Abstract: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.
    Type: Application
    Filed: June 23, 2008
    Publication date: October 23, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Takashi IPPOSHI, Toshiaki Iwamatsu, Shigeto Maegawa
  • Patent number: 7439587
    Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: October 21, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
  • Publication number: 20080179676
    Abstract: While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 31, 2008
    Inventors: Yuichi HIRANO, Takashi Ipposhi, Toshiaki Iwamatsu, Yukio Maki, Mikio Tsujiuchi
  • Patent number: 7402865
    Abstract: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: July 22, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu, Shigeto Maegawa
  • Patent number: 7393731
    Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
  • Publication number: 20080128814
    Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 5, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
  • Publication number: 20080128810
    Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 5, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
  • Publication number: 20080093669
    Abstract: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.
    Type: Application
    Filed: October 11, 2007
    Publication date: April 24, 2008
    Applicant: Renesas Technology Corp.
    Inventor: Toshiaki IWAMATSU
  • Patent number: 7358555
    Abstract: While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: April 15, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Tatsuhiko Ikeda, Shigeto Maegawa
  • Publication number: 20080081436
    Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 3, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Shigenobu MAEDA, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 7352049
    Abstract: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: April 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20080067593
    Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 20, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
  • Publication number: 20080061372
    Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Toshiaki Iwamatsu, Yuuiohi Hirano, Takashi Ipposhi
  • Publication number: 20080054414
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Application
    Filed: October 18, 2007
    Publication date: March 6, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Shigenobu MAEDA, Toshiaki IWAMATSU, Takashi IPPOSHI
  • Publication number: 20080050864
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Application
    Filed: October 18, 2007
    Publication date: February 28, 2008
    Applicant: RENESAS TECHNONOLY CORP.
    Inventors: Shigenobu MAEDA, Toshiaki IWAMATSU, Takashi IPPOSHI
  • Publication number: 20080042237
    Abstract: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a potion of the OSI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.
    Type: Application
    Filed: October 17, 2007
    Publication date: February 21, 2008
    Applicant: Renesas Technolgy Corp.
    Inventors: Toshiaki IWAMATSU, Takashi Ipposhi
  • Patent number: 7332776
    Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: February 19, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
  • Publication number: 20080035996
    Abstract: A semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer including, first and second element formation regions provided in said SOI layer, a partial isolation region including a partial insulating film provided in an upper layer portion of said SOI layer and a semiconductor region to be a part of said SOI layer which is provided under said partial insulating film and serving to isolate said first and second element formation regions from each other, and first and second MOS transistors formed in said first and second element formation regions, respectively, wherein at least one of a structure of a body region, a structure of a gate electrode and presence/absence of body potential fixation in said first and second MOS transistors is varied to make transistor characteristics of said first and second MOS transistors different from each other.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 14, 2008
    Applicant: Renesas Technology Corp.
    Inventors: TAKUJI MATSUMOTO, SHIGENOBU MAEDA, TOSHIAKI IWAMATSU, TAKASHI IPPOSHI
  • Publication number: 20080032486
    Abstract: A semiconductor wafer manufacturing method comprising the steps of preparing a first semiconductor wafer having a plurality of cuts formed at edge portions in crystal directions, preparing a second semiconductor wafer having a cut formed at an edge portion in a crystal direction that is different from the crystal direction of one of said plurality of cuts of said first semiconductor wafer, bonding said first and second semiconductor wafers to each other while using said one of said plurality of cuts of said first semiconductor wafer and said cut of said second semiconductor wafer in order to position said first and second semiconductor wafers, with another one of said plurality of cuts of said first semiconductor wafer being engaged with a guide portion of a semiconductor wafer manufacturing apparatus, thinning said first semiconductor wafer, implanting oxygen ions from said first semiconductor wafer side into a neighborhood of a part where said first and second semiconductor wafers are bonded to each other,
    Type: Application
    Filed: October 5, 2007
    Publication date: February 7, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Shigenobu Maeda