Patents by Inventor Toshiaki Iwamatsu

Toshiaki Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7723790
    Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
  • Patent number: 7692243
    Abstract: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Toshiaki Iwamatsu
  • Publication number: 20090194877
    Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.
    Type: Application
    Filed: March 6, 2009
    Publication date: August 6, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Yukio Maki, Takashi Ipposhi, Toshiaki Iwamatsu
  • Patent number: 7556997
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: July 7, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20090134468
    Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 28, 2009
    Inventors: Ryuta Tsuchiya, Toshiaki Iwamatsu
  • Publication number: 20090127623
    Abstract: In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.
    Type: Application
    Filed: January 16, 2009
    Publication date: May 21, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Mikio TSUJIUCHI, Toshiaki Iwamatsu, Shigeto Maegawa
  • Patent number: 7535062
    Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: May 19, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yukio Maki, Takashi Ipposhi, Toshiaki Iwamatsu
  • Publication number: 20090101977
    Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 23, 2009
    Inventors: Toshiaki Iwamatsu, Takashi Terada, Hirofumi Shinohara, Kozo Ishikawa, Ryuta Tsuchiya, Kiyoshi Hayashi
  • Publication number: 20090096036
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 16, 2009
    Inventors: Takashi ISHIGAKI, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii, Shinichiro Kimura, Toshiaki Iwamatsu
  • Patent number: 7511342
    Abstract: In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: March 31, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Mikio Tsujiuchi, Toshiaki Iwamatsu, Shigeto Maegawa
  • Patent number: 7504291
    Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20090051009
    Abstract: Formed on an insulator are an N? type semiconductor layer having a partial isolator formed on its surface and a P? type semiconductor layer having a partial isolator formed on its surface. Source/drain being P+ type semiconductor layers are provided on the semiconductor layer to form a PMOS transistor. Source/drain being N+ type semiconductor layers are provided on the semiconductor layer to form an NMOS transistor. A pn junction formed by the semiconductor layers is provided in a CMOS transistor made up of the transistors. The pn junction is positioned separately from the partial isolators where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction.
    Type: Application
    Filed: October 20, 2008
    Publication date: February 26, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
  • Patent number: 7494883
    Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: February 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto, Shigenobu Maeda
  • Publication number: 20090047757
    Abstract: In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.
    Type: Application
    Filed: October 17, 2008
    Publication date: February 19, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Mikio TSUJIUCHI, Toshiaki IWAMATSU, Takashi IPPOSHI
  • Patent number: 7482658
    Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: January 27, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
  • Publication number: 20090014797
    Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
    Type: Application
    Filed: September 11, 2008
    Publication date: January 15, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Yuuichi HIRANO, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
  • Patent number: 7470582
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: December 30, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20080315313
    Abstract: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Application
    Filed: October 3, 2007
    Publication date: December 25, 2008
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuo YAMAGUCHI, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Patent number: 7453135
    Abstract: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 7449749
    Abstract: Formed on an insulator (9) are an N? type semiconductor layer (10) having a partial isolator formed on its surface and a P? type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: November 11, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu