Abstract: A system and method is disclosed herein for providing column address increment pipelining within a single physically contiguous storage array, such as a left or a right unit of a double unit. Thereby, a multiple bank arrangement is provided within a double unit which permits column address increment pipelining to be performed within each bank thereof.

Abstract: A method and apparatus for eliminating defects present in memory devices by way of a defect management engine (DME) is described. The DME integrates a plurality of defective address cells and redundancy address cells within an array. The defective address cells store addresses for accessing defective cells in a main memory. The redundancy address cells store addresses for accessing redundancy cells within a redundancy memory. The address data in the defective address cells is compared to the address input of the DME, thereby providing a redundancy match detection scheme. When no match occurs, the DME outputs the address input of the DME, which allows the main memory to be accessed when operating in a normal mode. When a match occurs, the DME outputs the address read from the redundancy address cells, which allows the redundancy memory to be accessed when operating in a redundancy mode.

Abstract: A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

Abstract: A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted.

Abstract: A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Abstract: According to one aspect of the invention, there is provided a method for refreshing memory cells in semiconductor memories. The method includes the steps of providing a semiconductor memory having memory cells and redundancy memory cells in at least one memory array and an associated redundancy memory array, respectively. The memory cells and the redundancy memory cells are independently refreshed, using addresses generated by a row address counter and a redundancy address counter, respectively. The method optionally includes the step of disabling redundancy wordlines coupled to unused redundancy memory cells, using a master fuse signal corresponding to a master fuse of the semiconductor memory.

Abstract: An integrated circuit (IC) chip wherein a built-in self test determines the IC's optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the chip. Upon each chip power-up, the optimum performance setting is retrieved and provided to chip control which sets the chip for its best performance.

Abstract: A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and a sample wordline selector is coupled to activate the sample wordline or sample wordline redundancy based on the state of a nonvolatile input. The wordline selector circuit may include one or both of a row decoder circuit or a wordline driver circuit which have substantially the same structure and location as row decoder circuits and wordline driver circuits used to activate wordlines within the data-storing array region.

Abstract: A redundancy address in a plurality of memory devices is identified by at least two protocols available in an electric system. The first protocol is a mode register set command (or extended mode register set command). A chip select signal determines one of a plurality of memory modules, where a memory device is identified with at least one data port. Alternatively, a data strobe port or a data mask port may be preferably used for the selection of the memory devices instead of using the data port. The second protocol is a RAM access command which identifies a defective memory cell address (redundancy address) within the selected RAM by way of a plurality of address ports (ADRs). A redundancy address programming method is realized by way of electrically programmable fuses or by dynamically programmable redundancy latches integrated in each memory. The electric system configuration preferably includes a non-volatile storage device for storing a data port organization for the memory devices.

Abstract: A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially.

Abstract: A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses of the defective cells. The memories are preferably sub-divided into a plurality of domains. A plurality of defective cells in each domain are supported by a plurality of repair units, each consisting of one or more redundancy data bits and redundancy address bits in the DME. When one or more data bits are read from a domain in the memory, the corresponding wordline in the DME simultaneously activates a plurality of repair units coupling to the wordline (self-contained domain selection). The redundancy data bits and the redundancy address bits are also read from the redundancy data cells and redundancy address cells, respectively.

Abstract: A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more first pointer signals, each generated first pointer signal of a sequence corresponding to a specific latch device and overlapping in time with a prior generated first pointer signal of the sequence; and, a pulse converter device associated with a latch device for receiving a corresponding first pointer signal and generating a respective second pointer signal for input to a respective latch device, each second pointer signal generated in a non-overlapping sequence for triggering a respective latching of each data signal in synchronism with serially communicated data signals.

Abstract: A shared row decoder and shared row decoding method are disclosed herein which provides separate timed selection signals to each of a first memory unit and a second memory unit. The shared row decoder includes an address input circuit responsive to the states of a plurality of address signals and which provides an enabling or disabling input. In addition, first and second selection circuits are provided which are responsive to enabled conditions of first and second block selection inputs, first and second timing signals, respectively and enabling input of the address input circuit to provide separate timed selection signals to the first and second memory units, respectively.

Abstract: A method of performing overlapping operations with a memory device may have a sense amplifier circuit and two drivers connected to the sense amplifier circuit. Two data bus lines may be connected to the sense amplifier circuit to receive data signals. The method may include applying a first equalize signal and second equalize signal to the sense amplifier circuit to allow the sense amplifier circuit to receive the data signals across the data bus lines, applying a switch signal to the sense amplifier circuit to connect the data bus lines to a read data bus, and changing a state of the first equalize signal such that the data bus lines either receive new data or the data bus lines are equalized to a predetermined voltage while the data is on the read data bus and is capable of being read.

Abstract: A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.

Abstract: A memory (e.g. , Dynamic Random Access Memory (DRAM)) with self-programmable Built In Self Test (BIST). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Abstract: An integrated circuit device including a conductor-insulator-conductor structure and a method of manufacturing the structure simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings extend through a second interlevel dielectric to the first interconnect layer. An insulator is deposited in the openings. A trench is then etched into the upper portion of the openings that will become vias while simultaneously removing the insulator from the bottom of the openings that will become vias. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

Abstract: The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.