Abstract: A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data at the output is preferably compared to expected data. Alternately, system level calibration between devices may be performed to ensure proper communication between devices without destroying data in a memory array and making a dynamic data skew calibration possibly while running an application.

Abstract: A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.

Abstract: Gain cells adapted to trench capacitor technology and memory array configured with these gain cells are described. The 3T and 2T gain cells of the present invention include a trench capacitor attached to a storage node such that the storage voltage is maintained for a long retention time. The gate of the gain transistor and the trench capacitor are placed alongside the read and write wordline. This arrangement makes it possible to have the gain transistor directly coupled to the trench capacitor, resulting in a smaller cell size.

Abstract: A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

Abstract: Multiple conductive paths are provided in a circuit portion between a circuit element and a logic block, enabling repairing of defects in the conductive line coupling the circuit element and logic blocks without the use of fusing.

Abstract: A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell.

Abstract: A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell.

Abstract: An improved memory array having adjacent banks with diagonal bitlines is disclosed. The memory banks include respective memory blocks which are adjacent to each other. The memory blocks comprises diagonal bitlines and twist regions which change the directions of the diagonal bitlines, forming zigzagged sides along the general direction of the bitlines. The bitlines of the adjacent blocks run in the same direction in order to reduce unused area caused by the zigzagged sides of the memory blocks.

Abstract: Digital latency shift communication problems from a driver chip to a receiver chip are overcome by scheduling a data output latency, a data input latency, a data output command, and/or a data output command, such that data outputted by the driver chip is received by the receiver chip at the correct time. A digital shift detection circuit detects the offset of the actual latencies from predetermined latencies. The offset of the latency is fed back to the scheduling circuit to override the predetermined latencies and/or command inputs that control the chip. The offset can be directly back-fed to the chip driver or chip receiver to compensate for digital shifts. Digital shift detection is achieved by measuring actual latencies with a manufacturing stand-alone tester, or with a built-in tester integral to the system. The digital shift detection predicts the conditions that create a digital shift by way of a mathematical model.

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

Abstract: A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

Abstract: A method for preparing a dynamic random access memory (DRAM) cell for a write operation with a preset condition is disclosed. In an exemplary embodiment, the method includes creating a preset voltage level within the cell prior to a delayed write back in a destructive read architecture, which preset voltage level has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when the cell has a 0 bit stored therein, and the logic 1 voltage level corresponds to a second cell voltage value when the cell has a 1 bit stored therein. Prior to the creation of the preset voltage level within the cell, the cell has an initial voltage value corresponding to either the logic 0 voltage level or the logic 1 voltage level.

Abstract: A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area.

Abstract: Multiple conductive paths are provided in a circuit portion between a circuit element and a logic block, enabling repairing of defects in the conductive line coupling the circuit element and logic blocks without the use of fusing.

Abstract: A memory block with improved access time is disclosed. The memory block comprises a plurality of cells interconnected by bitlines in a first direction and wordlines in a second direction. A column decoder is located on a first side of the array along the second direction and a sense amplifier along a second side opposite the first side, resulting in access time reduced by about half compared to conventional memory blocks.

Abstract: A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

Abstract: A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area.

Abstract: A memory structure comprises a plurality of banks (each of the banks including a plurality of blocks) a plurality of timing critical address lines connected to all of the blocks in respective ones of the banks (a number of the critical address lines being equal to a number of the banks), and a plurality of dedicated address lines connected to respective ones of the blocks.