Patents by Inventor Toshiaki Kirihata

Toshiaki Kirihata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

Address wrap function for addressable memory devices

Patent number: 7061821

Abstract: The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array. Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes. The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.

Type: Grant

Filed: February 6, 2002

Date of Patent: June 13, 2006

Assignee: International Business Machines Corporation

Inventors: Paul William Coteus, William Paul Hovis, William Wu Shen, Toshiaki Kirihata
Multi-port memory architecture

Patent number: 6990025

Abstract: A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors.

Type: Grant

Filed: August 29, 2003

Date of Patent: January 24, 2006

Assignee: International Business Machines Corporation

Inventors: Toshiaki Kirihata, Hoki Kim, Matthew Wordeman
Concurrent refresh mode with distributed row address counters in an embedded DRAM

Patent number: 6967885

Abstract: A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

Type: Grant

Filed: January 15, 2004

Date of Patent: November 22, 2005

Assignee: International Business Machines Corporation

Inventors: John E. Barth, Jr., Toshiaki Kirihata, Paul C. Parries
DESTRUCTIVE-READ RANDOM ACCESS MEMORY SYSTEM BUFFERED WITH DESTRUCTIVE-READ MEMORY CACHE

Publication number: 20050226083

Abstract: A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.

Type: Application

Filed: June 14, 2005

Publication date: October 13, 2005

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventors: Brian Ji, Chorng-Lii Hwang, Toshiaki Kirihata, Seiji Munetoh
Dynamic random access memory with smart refresh scheduler

Patent number: 6954387

Abstract: In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

Type: Grant

Filed: July 15, 2003

Date of Patent: October 11, 2005

Assignee: International Business Machines Corporation

Inventors: Hoki Kim, Toshiaki Kirihata, David R. Hanson, Gregory J. Fredeman, John Golz
Cell data margin test with dummy cell

Patent number: 6950353

Abstract: A memory array includes a true bitline and a complementary bitline and a sense amplifier connected thereto; a row of normal cells with capacitors for data storage and bitline storage capacitors. A row of dummy cells with dummy cell capacitors is also provided. A clock provides wordline drive signals to the normal cells. When operating in the test mode, the clock provides at least one dummy wordline drive signal to the dummy cell switch in response to a testing signal for connecting the dummy cell capacitor to the bitline. A plurality of rows of dummy cells can be employed with various permutations of actuation thereof to provide various levels of capacitance connected to the bitlines in the test mode.

Type: Grant

Filed: February 1, 2005

Date of Patent: September 27, 2005

Assignee: International Business Machines Corporation

Inventors: Hoki Kim, Toshiaki Kirihata
Gain cell memory having read cycle interlock

Patent number: 6947348

Abstract: A method is provided for accessing a storage cell of a dynamic random access memory (DRAM) having an array of gain cells being read accessible by a read wordline and a read bitline, and being write accessible by a write wordline and write bitline separate from said read wordline and read bitline. The method includes activating a read wordline of the array of gain cells to permit signals from a plurality of gain cells coupled to the read wordline to develop on a plurality of corresponding read bitlines coupled to the gain cells. An interlock signal is then generated in the DRAM after activating the read wordline. The read wordline is then deactivated in response to the interlock signal.

Type: Grant

Filed: July 15, 2003

Date of Patent: September 20, 2005

Assignee: International Business Machines Corporation

Inventors: Hoki Kim, Toshiaki Kirihata
A Command Multiplier for Built-In-Self-Test

Publication number: 20050193253

Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

Type: Application

Filed: February 13, 2004

Publication date: September 1, 2005

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventors: Jonathan Fales, Gregory Fredeman, Kevin Gorman, Mark Jacunski, Toshiaki Kirihata, Alan Norris, Paul Parries, Matthew Wordeman
Method and structure for enabling a redundancy allocation during a multi-bank operation

Publication number: 20050180230

Abstract: A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.

Type: Application

Filed: February 12, 2004

Publication date: August 18, 2005

Inventors: Gregory Fredeman, Mark Jacunski, Toshiaki Kirihata, Matthew Wordeman
Concurrent refresh mode with distributed row address counters in an embedded DRAM

Publication number: 20050157577

Abstract: A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

Type: Application

Filed: January 15, 2004

Publication date: July 21, 2005

Inventors: John Barth, Toshiaki Kirihata, Paul Parries
System and method for variable array architecture for memories

Publication number: 20050144373

Abstract: A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

Type: Application

Filed: December 31, 2003

Publication date: June 30, 2005

Inventors: Toshiaki Kirihata, Gerhard Mueller, Wing Luk
Flexible row redundancy system

Publication number: 20050122801

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Type: Application

Filed: January 7, 2005

Publication date: June 9, 2005

Applicant: International Business Machines Corporation

Inventors: Louis Hsu, Gregory Fredeman, Rajiv Joshi, Toshiaki Kirihata
MULTI-PORT MEMORY ARCHITECTURE

Publication number: 20050047218

Abstract: A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors.

Type: Application

Filed: August 29, 2003

Publication date: March 3, 2005

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventors: Toshiaki Kirihata, Hoki Kim, Matthew Wordeman
GAIN CELL MEMORY HAVING READ CYCLE INTERLOCK

Publication number: 20050024923

Abstract: A method is provided for accessing a storage cell of a dynamic random access memory (DRAM) having an array of gain cells being read accessible by a read wordline and a read bitline, and being write accessible by a write wordline and write bitline separate from said read wordline and read bitline. The method includes activating a read wordline of the array of gain cells to permit signals from a plurality of gain cells coupled to the read wordline to develop on a plurality of corresponding read bitlines coupled to the gain cells. An interlock signal is then generated in the DRAM after activating the read wordline. The read wordline is then deactivated in response to the interlock signal.

Type: Application

Filed: July 15, 2003

Publication date: February 3, 2005

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventors: Hoki Kim, Toshiaki Kirihata
DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER

Publication number: 20050013185

Abstract: In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

Type: Application

Filed: July 15, 2003

Publication date: January 20, 2005

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventors: Hoki Kim, Toshiaki Kirihata, David Hanson, Gregory Fredeman, John Golz
Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology

Patent number: 6845033

Abstract: A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.

Type: Grant

Filed: March 5, 2003

Date of Patent: January 18, 2005

Assignee: International Business Machines Corporation

Inventors: Toshiaki Kirihata, John W. Golz
High performance gain cell architecture

Patent number: 6845059

Abstract: A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle.

Type: Grant

Filed: June 26, 2003

Date of Patent: January 18, 2005

Assignee: International Business Machines Corporation

Inventors: Matthew R. Wordeman, John E. Barth, Toshiaki Kirihata
Output driver impedance control for addressable memory devices

Publication number: 20050002223

Abstract: A selectable function is provided that permits the impedance of an output driver or an addressable memory device to be configured without adding extra signal connections. The output driver impedance control function of the invention is achieved through the use of the data bus of a memory array for control. The data lines thus serve two purposes one for normal use and the other for control of the impedance. In the invention, the output impedance of each DRAM in a subassembly array that drives a common data bus is individually separately adjusted.

Type: Application

Filed: October 17, 2003

Publication date: January 6, 2005

Inventors: Paul Coteus, Brian Ji, Toshiaki Kirihata, Joseph Macri, John Ross
HIGH PERFORMANCE GAIN CELL ARCHITECTURE

Publication number: 20040264279

Abstract: A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle.

Type: Application

Filed: June 26, 2003

Publication date: December 30, 2004

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventors: Matthew R. Wordeman, John E. Barth, Toshiaki Kirihata
Destructive read architecture for dynamic random access memories

Patent number: 6829682

Abstract: A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.

Type: Grant

Filed: April 26, 2001

Date of Patent: December 7, 2004

Assignee: International Business Machines Corporation

Inventors: Toshiaki Kirihata, Sang Hoo Dhong, Hwa-Joon Oh, Matthew Wordeman

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