Patents by Inventor Toshihiko Takeuchi

Toshihiko Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12154827
    Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: November 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Tsutomu Murakawa, Hiroki Komagata, Daisuke Matsubayashi, Noritaka Ishihara, Yusuke Nonaka
  • Publication number: 20240317816
    Abstract: The disclosure provides peptides, pharmaceutical compositions, and methods of producing thereof. Such peptides can be useful, for example, in treating various human diseases such as immunological diseases or cancers. In some embodiments, the peptides are useful as immunotherapeutics for modulating regulatory and effector molecules of the mammalian immune system.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 26, 2024
    Inventors: Helena Kiefel, Dhwani Haria, Michi Izumi Willcoxon, Kyle Roskamp, Toshihiko Takeuchi, Karim Dabbagh
  • Publication number: 20240304728
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Application
    Filed: April 18, 2024
    Publication date: September 12, 2024
    Inventors: Toshihiko TAKEUCHI, Naoto YAMADE, Yutaka OKAZAKI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Patent number: 12071475
    Abstract: The present disclosure relates, in general, to materials and methods for antibodies specific for transforming growth factor beta (TGF?), including TGF?1, TGF?2 and TGF?3, and uses of these antibodies in the treatment of subjects having cancer, an eye disease, condition or disorder, fibrosis, including ophthalmic fibrosis or fibrosis of the eye, and other conditions or disorders related to TGF? expression.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 27, 2024
    Assignee: XOMA TECHNOLOGY LTD.
    Inventors: Daniel H. Bedinger, Shireen S. Khan, Amer M. Mirza, Ajay J. Narasimha, Toshihiko Takeuchi
  • Publication number: 20240258409
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first conductor, a second conductor over the first conductor, a first insulator covering the second conductor, a first oxide over the first insulator, and a second oxide over the first oxide, an opening overlapping with at least part of the first conductor is provided in the first oxide and the first insulator, and the second oxide is electrically connected to the first conductor through the opening.
    Type: Application
    Filed: April 2, 2024
    Publication date: August 1, 2024
    Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Naoto YAMADE, Hiroshi FUJIKI, Tomoaki MORIWAKA, Shunsuke KIMURA
  • Publication number: 20240183054
    Abstract: To form graphene to a practically even thickness on an object having an uneven surface or a complex surface, in particular, an object having a surface with a three-dimensional structure due to complex unevenness, or an object having a curved surface. The object and an electrode are immersed in a graphene oxide solution, and voltage is applied between the object and the electrode. At this time, the object serves as an anode. Graphene oxide is attracted to the anode because of being negatively charged, and deposited on the surface of the object to have a practically even thickness. A portion where graphene oxide is deposited is unlikely coated with another graphene oxide. Thus, deposited graphene oxide is reduced to graphene, whereby graphene can be formed to have a practically even thickness on an object having surface with complex unevenness.
    Type: Application
    Filed: February 9, 2024
    Publication date: June 6, 2024
    Inventors: Teppei OGUNI, Takeshi OSADA, Toshihiko TAKEUCHI
  • Publication number: 20240158535
    Abstract: The present disclosure relates, in general, human antibodies against human parathyroid hormone receptor 1 (PTH1R) and methods of use of such antibodies in the treatment of cancer, Humoral Hypercalcemia of Malignancy (HHM), or Primary Hyperparathyroidism (PHPT) and Secondary Hyperparathyroidism (SHPT) and cachexia.
    Type: Application
    Filed: September 7, 2023
    Publication date: May 16, 2024
    Inventors: Raphael D. Levy, Hassan Issafras, Agnes Choppin Holmes, Kirk W. Johnson, Amer M. Mirza, Daniel H. Bedinger, Rachel A. Hunt, Toshihiko Takeuchi, Kiranjit Kaur Ahluwalia, Robyn Cotter
  • Patent number: 11967649
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Takeuchi, Naoto Yamade, Yutaka Okazaki, Sachiaki Tezuka, Shunpei Yamazaki
  • Patent number: 11955538
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first conductor, a second conductor over the first conductor, a first insulator covering the second conductor, a first oxide over the first insulator, and a second oxide over the first oxide, an opening overlapping with at least part of the first conductor is provided in the first oxide and the first insulator, and the second oxide is electrically connected to the first conductor through the opening.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: April 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Naoto Yamade, Hiroshi Fujiki, Tomoaki Moriwaka, Shunsuke Kimura
  • Publication number: 20240088232
    Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Kosei NEI, Tsutomu MURAKAWA, Toshihiko TAKEUCHI, Kentaro SUGAYA
  • Publication number: 20240066095
    Abstract: The disclosure relates to therapeutic proteins and pharmaceutical compositions comprising said proteins, which have utility in treating various human diseases. In particular aspects, the disclosed therapeutic proteins are useful for treating human gastrointestinal inflammatory diseases and gastrointestinal conditions associated with decreased epithelial cell barrier function or integrity. Further, the disclosed therapeutic proteins are useful for treating human inflammatory bowel disease, including inter alia, Crohn's disease and ulcerative colitis.
    Type: Application
    Filed: April 24, 2023
    Publication date: February 29, 2024
    Inventors: Andrew Wonhee Han, Andrew Whitman Goodyear, Tarunmeet Gujral, Todd Zachary DeSantis, Karim Dabbagh, Toshihiko Takeuchi, Ye Jin, Michi Izumi Willcoxon, Stefanie Banas
  • Publication number: 20240055299
    Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Daisuke MATSUBAYASHI, Noritaka ISHIHARA, Yusuke NONAKA
  • Patent number: 11898261
    Abstract: To form graphene to a practically even thickness on an object having an uneven surface or a complex surface, in particular, an object having a surface with a three-dimensional structure due to complex unevenness, or an object having a curved surface. The object and an electrode are immersed in a graphene oxide solution, and voltage is applied between the object and the electrode. At this time, the object serves as an anode. Graphene oxide is attracted to the anode because of being negatively charged, and deposited on the surface of the object to have a practically even thickness. A portion where graphene oxide is deposited is unlikely coated with another graphene oxide. Thus, deposited graphene oxide is reduced to graphene, whereby graphene can be formed to have a practically even thickness on an object having surface with complex unevenness.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: February 13, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Teppei Oguni, Takeshi Osada, Toshihiko Takeuchi
  • Patent number: 11881513
    Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: January 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Nei, Tsutomu Murakawa, Toshihiko Takeuchi, Kentaro Sugaya
  • Publication number: 20240006539
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Inventors: Shunpei YAMAZAKI, Hiromi SAWAI, Ryo TOKUMARU, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Sho NAGAMATSU, Tomoaki MORIWAKA
  • Publication number: 20230352687
    Abstract: Graphene is formed with a practically uniform thickness on an uneven object. The object is immersed in a graphene oxide solution, and then taken out of the solution and dried; alternatively, the object and an electrode are immersed therein and voltage is applied between the electrode and the object used as an anode. Graphene oxide is negatively charged, and thus is drawn to and deposited on a surface of the object, with a practically uniform thickness. After that, the object is heated in vacuum or a reducing atmosphere, so that the graphene oxide is reduced to be graphene. In this manner, a graphene layer with a practically uniform thickness can be formed even on a surface of the uneven object.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Teppei OGUNI, Takeshi OSADA, Toshihiko TAKEUCHI, Kuniharu NOMOTO
  • Patent number: 11804407
    Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: October 31, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Tsutomu Murakawa, Hiroki Komagata, Daisuke Matsubayashi, Noritaka Ishihara, Yusuke Nonaka
  • Patent number: 11787876
    Abstract: The present disclosure relates, in general, human antibodies against human parathyroid hormone receptor 1 (PTH1R) and methods of use of such antibodies in the treatment of cancer, Humoral Hypercalcemia of Malignancy (HHM), or Primary Hyperparathyroidism (PHPT) and Secondary Hyperparathyroidism (SHPT) and cachexia.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 17, 2023
    Assignee: XOMA (US) LLC
    Inventors: Raphael D. Levy, Hassan Issafras, Agnes Choppin Holmes, Kirk W. Johnson, Amer M. Mirza, Daniel H. Bedinger, Rachel A. Hunt, Toshihiko Takeuchi, Kiranjit Kaur Ahluwalia, Robyn Cotter
  • Patent number: 11784259
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: October 10, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromi Sawai, Ryo Tokumaru, Toshihiko Takeuchi, Tsutomu Murakawa, Sho Nagamatsu, Tomoaki Moriwaka
  • Publication number: 20230299183
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first conductor, a second conductor over the first conductor, a first insulator covering the second conductor, a first oxide over the first insulator, and a second oxide over the first oxide, an opening overlapping with at least part of the first conductor is provided in the first oxide and the first insulator, and the second oxide is electrically connected to the first conductor through the opening.
    Type: Application
    Filed: April 18, 2023
    Publication date: September 21, 2023
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Naoto YAMADE, Hiroshi FUJIKI, Tomoaki MORIWAKA, Shunsuke KIMURA