Patents by Inventor Toshihiko Takeuchi

Toshihiko Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11666627
    Abstract: The disclosure relates to therapeutic proteins and pharmaceutical compositions comprising said proteins, which have utility in treating various human diseases. In particular aspects, the disclosed therapeutic proteins are useful for treating human gastrointestinal inflammatory diseases and gastrointestinal conditions associated with decreased epithelial cell barrier function or integrity. Further, the disclosed therapeutic proteins are useful for treating human inflammatory bowel disease, including inter alia, Crohn's disease and ulcerative colitis.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 6, 2023
    Assignee: Second Genome, Inc.
    Inventors: Andrew Wonhee Han, Andrew Whitman Goodyear, Tarunmeet Gujral, Todd Zachary Desantis, Karim Dabbagh, Toshihiko Takeuchi, Ye Jin, Michi Izumi Willcoxon, Stefanie Banas
  • Patent number: 11600705
    Abstract: A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), IOFF represents the off-state current, t represents time during which the transistor is off, ? and ? are constants, ? is a constant that satisfies 0<??1, and CS is a constant that represents load capacitance of a source or a drain.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 7, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masashi Tsubuku, Shunpei Yamazaki, Hidetomo Kobayashi, Kazuaki Ohshima, Masashi Fujita, Toshihiko Takeuchi
  • Publication number: 20220416089
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Application
    Filed: August 25, 2022
    Publication date: December 29, 2022
    Inventors: Toshihiko TAKEUCHI, Naoto YAMADE, Yutaka OKAZAKI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Patent number: 11495691
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: November 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Takeuchi, Naoto Yamade, Yutaka Okazaki, Sachiaki Tezuka, Shunpei Yamazaki
  • Publication number: 20220336670
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.
    Type: Application
    Filed: March 17, 2022
    Publication date: October 20, 2022
    Inventors: Shunpei YAMAZAKI, Hiromi SAWAI, Ryo TOKUMARU, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Sho NAGAMATSU, Tomoaki MORIWAKA
  • Patent number: 11404585
    Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: August 2, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Tetsuhiro Tanaka, Toshihiko Takeuchi, Yasumasa Yamane, Takayuki Inoue, Shunpei Yamazaki
  • Publication number: 20220223866
    Abstract: Graphene is formed with a practically uniform thickness on an uneven object. The object is immersed in a graphene oxide solution, and then taken out of the solution and dried; alternatively, the object and an electrode are immersed therein and voltage is applied between the electrode and the object used as an anode. Graphene oxide is negatively charged, and thus is drawn to and deposited on a surface of the object, with a practically uniform thickness. After that, the object is heated in vacuum or a reducing atmosphere, so that the graphene oxide is reduced to be graphene. In this manner, a graphene layer with a practically uniform thickness can be formed even on a surface of the uneven object.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Inventors: Teppei OGUNI, Takeshi OSADA, Toshihiko TAKEUCHI, Kuniharu NOMOTO
  • Publication number: 20220127746
    Abstract: To form graphene to a practically even thickness on an object having an uneven surface or a complex surface, in particular, an object having a surface with a three-dimensional structure due to complex unevenness, or an object having a curved surface. The object and an electrode are immersed in a graphene oxide solution, and voltage is applied between the object and the electrode. At this time, the object serves as an anode. Graphene oxide is attracted to the anode because of being negatively charged, and deposited on the surface of the object to have a practically even thickness. A portion where graphene oxide is deposited is unlikely coated with another graphene oxide. Thus, deposited graphene oxide is reduced to graphene, whereby graphene can be formed to have a practically even thickness on an object having surface with complex unevenness.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Inventors: Teppei OGUNI, Takeshi OSADA, Toshihiko TAKEUCHI
  • Patent number: 11296322
    Abstract: Graphene is formed with a practically uniform thickness on an uneven object. The object is immersed in a graphene oxide solution, and then taken out of the solution and dried; alternatively, the object and an electrode are immersed therein and voltage is applied between the electrode and the object used as an anode. Graphene oxide is negatively charged, and thus is drawn to and deposited on a surface of the object, with a practically uniform thickness. After that, the object is heated in vacuum or a reducing atmosphere, so that the graphene oxide is reduced to be graphene. In this manner, a graphene layer with a practically uniform thickness can be formed even on a surface of the uneven object.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 5, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Teppei Oguni, Takeshi Osada, Toshihiko Takeuchi, Kuniharu Nomoto
  • Patent number: 11282964
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromi Sawai, Ryo Tokumaru, Toshihiko Takeuchi, Tsutomu Murakawa, Sho Nagamatsu, Tomoaki Moriwaka
  • Publication number: 20220059409
    Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Daisuke MATSUBAYASHI, Noritaka ISHIHARA, Yusuke NONAKA
  • Patent number: 11248307
    Abstract: To form graphene to a practically even thickness on an object having an uneven surface or a complex surface, in particular, an object having a surface with a three-dimensional structure due to complex unevenness, or an object having a curved surface. The object and an electrode are immersed in a graphene oxide solution, and voltage is applied between the object and the electrode. At this time, the object serves as an anode. Graphene oxide is attracted to the anode because of being negatively charged, and deposited on the surface of the object to have a practically even thickness. A portion where graphene oxide is deposited is unlikely coated with another graphene oxide. Thus, deposited graphene oxide is reduced to graphene, whereby graphene can be formed to have a practically even thickness on an object having surface with complex unevenness.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: February 15, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Teppei Oguni, Takeshi Osada, Toshihiko Takeuchi
  • Patent number: 11207376
    Abstract: The disclosure relates to therapeutic proteins and pharmaceutical compositions comprising said proteins, which have utility in treating various human diseases. In particular aspects, the disclosed therapeutic proteins are useful for treating human gastrointestinal inflammatory diseases and gastrointestinal conditions associated with decreased epithelial cell barrier function or integrity. Further, the disclosed therapeutic proteins are useful for treating human inflammatory bowel disease, including inter alia, Crohn's disease and ulcerative colitis.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: December 28, 2021
    Assignee: Second Genome, Inc.
    Inventors: Andrew Wonhee Han, Andrew Whitman Goodyear, Tarunmeet Gujral, Todd Zachary Desantis, Karim Dabbagh, Toshihiko Takeuchi, Ye Jin, Michi Izumi Willcoxon, Stefanie Banas
  • Patent number: 11211500
    Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a first conductor and a second conductor over the second oxide, a third oxide over the second oxide, a second insulator over the third oxide, a third conductor that is located over the second insulator and overlaps with the third oxide, a third insulator that is located over the first insulator and in contact with a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor, and a fourth insulator over the third conductor, the second insulator, the third oxide, and the third insulator. The fourth insulator is in contact with a top surface of each of the third conductor, the second insulator, and the third oxide.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromi Sawai, Ryo Tokumaru, Toshihiko Takeuchi, Tsutomu Murakawa, Sho Nagamatsu, Tomoaki Moriwaka
  • Patent number: 11195758
    Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 7, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Tsutomu Murakawa, Hiroki Komagata, Daisuke Matsubayashi, Noritaka Ishihara, Yusuke Nonaka
  • Publication number: 20210355204
    Abstract: The present disclosure relates, in general, to materials and methods for antibodies specific for transforming growth factor beta (TGF?), including TGF?1, TGF?2 and TGF?3, and uses of these antibodies in the treatment of subjects having cancer, an eye disease, condition or disorder, fibrosis, including ophthalmic fibrosis or fibrosis of the eye, and other conditions or disorders related to TGF? expression.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 18, 2021
    Inventors: Daniel H. Bedinger, Shireen S. Khan, Amer M. Mirza, Ajay J. Narasimha, Toshihiko Takeuchi
  • Patent number: 11177176
    Abstract: A semiconductor device that can have favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; a second insulator over the first insulator; an oxide over the second insulator; a first conductor and a second conductor over the oxide; a third insulator over the oxide; a third conductor positioned over the third insulator and overlapping with the oxide; a fourth insulator in contact with the second insulator, a side surface of the oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, a top surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with a top surface of the third insulator and a top surface of the third conductor, and a top surface of the fourth insulator is in contact with the fifth insulator.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: November 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Hiromi Sawai, Ryota Hodo, Katsuaki Tochibayashi
  • Patent number: 11098111
    Abstract: The present disclosure relates, in general, to materials and methods for antibodies specific for transforming growth factor beta (TGF?), including TGF?1, TGF?2 and TGF?3, and uses of these antibodies in the treatment of subjects having cancer, an eye disease, condition or disorder, fibrosis, including ophthalmic fibrosis or fibrosis of the eye, and other conditions or disorders related to TGF? expression.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: August 24, 2021
    Assignee: XOMA TECHNOLOGY LTD.
    Inventors: Daniel Bedinger, Shireen S. Khan, Amer Mirza, Ajay J. Narasimha, Toshihiko Takeuchi
  • Publication number: 20210210635
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.
    Type: Application
    Filed: November 26, 2018
    Publication date: July 8, 2021
    Inventors: Shunpei YAMAZAKI, Hiromi SAWAI, Ryo TOKUMARU, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Sho NAGAMATSU, Tomoaki MORIWAKA
  • Publication number: 20210210640
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Application
    Filed: May 27, 2019
    Publication date: July 8, 2021
    Inventors: Toshihiko TAKEUCHI, Naoto YAMADE, Yutaka OKAZAKI, Sachiaki TEZUKA, Shunpei YAMAZAKI