Patents by Inventor Toshihiro Ohki
Toshihiro Ohki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190051579Abstract: A semiconductor device includes a semiconductor chip including a substrate and an element region on the substrate, a heat transfer body made of diamond, and a metal layer between the semiconductor chip and the heat transfer body, wherein the substrate includes an amorphous region on a back surface thereof, the amorphous region and the metal layer are bonded to each other, and the metal layer and the heat transfer body are bonded to each other.Type: ApplicationFiled: July 24, 2018Publication date: February 14, 2019Applicant: FUJITSU LIMITEDInventors: Yuichi Minoura, Naoya Okamoto, Toshihiro Ohki
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Patent number: 9685547Abstract: A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film.Type: GrantFiled: May 23, 2016Date of Patent: June 20, 2017Assignee: FUJITSU LIMITEDInventor: Toshihiro Ohki
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Patent number: 9647084Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.Type: GrantFiled: December 11, 2015Date of Patent: May 9, 2017Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
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Publication number: 20170104098Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Applicant: FUJITSU LIMITEDInventors: Toshihiro OHKI, Masato NISHIMORI, Tadahiro IMADA
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Patent number: 9608083Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.Type: GrantFiled: June 9, 2015Date of Patent: March 28, 2017Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
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Patent number: 9564527Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.Type: GrantFiled: April 24, 2013Date of Patent: February 7, 2017Assignee: FUJITSU LIMITEDInventors: Toshihiro Ohki, Masato Nishimori, Tadahiro Imada
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Patent number: 9553152Abstract: A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.Type: GrantFiled: December 4, 2014Date of Patent: January 24, 2017Assignee: FUJITSU LIMITEDInventors: Toshihiro Ohki, Lei Zhu, Naoya Okamoto, Yuichi Minoura, Shirou Ozaki
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Patent number: 9496380Abstract: At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.Type: GrantFiled: December 16, 2011Date of Patent: November 15, 2016Assignee: FUJITSU LIMITEDInventors: Yuichi Minoura, Toshihide Kikkawa, Toshihiro Ohki
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Publication number: 20160268412Abstract: A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film.Type: ApplicationFiled: May 23, 2016Publication date: September 15, 2016Applicant: FUJITSU LIMITEDInventor: Toshihiro OHKI
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Patent number: 9379229Abstract: A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film.Type: GrantFiled: February 23, 2012Date of Patent: June 28, 2016Assignee: FUJITSU LIMITEDInventor: Toshihiro Ohki
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Publication number: 20160099335Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Applicant: FUJITSU LIMITEDInventors: Shirou OZAKI, Naoya OKAMOTO, Kozo MAKIYAMA, Toshihiro OHKI
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Patent number: 9276100Abstract: A semiconductor device includes a first semiconductor layer disposed over a substrate, a second semiconductor layer disposed over the first semiconductor layer, a gate recess disposed, through removal of a part of or all the second semiconductor layer, in a predetermined region over the first semiconductor layer, an insulating film disposed over the gate recess and the second semiconductor layer, a gate electrode disposed over the gate recess with the insulating film therebetween, and a source electrode and a drain electrode disposed over the first semiconductor layer or the second semiconductor layer, whereby a central portion of the gate recess is higher than a peripheral portion of the gate recess.Type: GrantFiled: November 11, 2011Date of Patent: March 1, 2016Assignee: FUJITSU LIMITEDInventors: Hiroshi Endo, Toshihiro Ohki, Toshihide Kikkawa
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Patent number: 9269782Abstract: A semiconductor device, comprising: a first semiconductor layer disposed on a substrate; a second semiconductor layer disposed on the first semiconductor layer; a lower insulating film disposed on the second semiconductor layer; a p-type electroconductive oxide film disposed on the lower insulating film; an upper insulating film disposed on the oxide film; and a gate electrode disposed on the upper insulating film, wherein the lower insulating film under the gate electrode has a depressed portion.Type: GrantFiled: September 7, 2012Date of Patent: February 23, 2016Assignee: FUJITSU LIMITEDInventors: Masahito Kanamura, Toyoo Miyajima, Toshihiro Ohki
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Patent number: 9257514Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.Type: GrantFiled: March 19, 2014Date of Patent: February 9, 2016Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
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Patent number: 9209042Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.Type: GrantFiled: June 11, 2014Date of Patent: December 8, 2015Assignee: FUJITSU LIMITEDInventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
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Publication number: 20150279956Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.Type: ApplicationFiled: June 9, 2015Publication date: October 1, 2015Applicant: FUJITSU LIMITEDInventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
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Patent number: 9123793Abstract: A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed.Type: GrantFiled: August 4, 2014Date of Patent: September 1, 2015Assignee: FUJITSU LIMITEDInventors: Toshihiro Ohki, Hiroshi Endo
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Patent number: 9099351Abstract: A compound semiconductor device includes as compound semiconductor layers: a first layer; a second layer larger in band gap than the first layer, formed above the first layer; a third layer having a p-type conductivity type, formed above the second layer; a gate electrode formed above the second layer via the third layer; a fourth layer larger in band gap than the second layer, formed to be in contact with the third layer above the second layer; and a fifth layer smaller in band gap than the fourth layer, formed to be in contact with the third layer above the fourth layer.Type: GrantFiled: July 16, 2013Date of Patent: August 4, 2015Assignee: Transphorm Japan, Inc.Inventors: Masato Nishimori, Tadahiro Imada, Toshihiro Ohki
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Patent number: 9093512Abstract: A compound semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a source electrode and a drain electrode provided over the nitride semiconductor stacked structure; a gate electrode provided between the source electrode and the drain electrode, over the nitride semiconductor stacked structure; a field plate provided at least partially between the gate electrode and the drain electrode; and a plurality of insulation films and formed over the nitride semiconductor stacked structure, wherein a number of interfaces of the plurality of insulation films is smaller between the field plate and the drain electrode than in the vicinity of the gate electrode.Type: GrantFiled: December 14, 2011Date of Patent: July 28, 2015Assignee: FUJITSU LIMITEDInventor: Toshihiro Ohki
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Publication number: 20150194512Abstract: A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.Type: ApplicationFiled: December 4, 2014Publication date: July 9, 2015Applicant: FUJITSU LIMITEDInventors: Toshihiro Ohki, LEI ZHU, NAOYA OKAMOTO, Yuichi Minoura, Shirou OZAKI