Patents by Inventor Toshihiro Ohki

Toshihiro Ohki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9647084
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 9, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
  • Publication number: 20170104098
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.
    Type: Application
    Filed: December 21, 2016
    Publication date: April 13, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro OHKI, Masato NISHIMORI, Tadahiro IMADA
  • Patent number: 9608083
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Patent number: 9564527
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Masato Nishimori, Tadahiro Imada
  • Patent number: 9553152
    Abstract: A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 24, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Lei Zhu, Naoya Okamoto, Yuichi Minoura, Shirou Ozaki
  • Patent number: 9496380
    Abstract: At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 15, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Toshihide Kikkawa, Toshihiro Ohki
  • Publication number: 20160268412
    Abstract: A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Toshihiro OHKI
  • Patent number: 9379229
    Abstract: A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: June 28, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiro Ohki
  • Publication number: 20160099335
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Naoya OKAMOTO, Kozo MAKIYAMA, Toshihiro OHKI
  • Patent number: 9276100
    Abstract: A semiconductor device includes a first semiconductor layer disposed over a substrate, a second semiconductor layer disposed over the first semiconductor layer, a gate recess disposed, through removal of a part of or all the second semiconductor layer, in a predetermined region over the first semiconductor layer, an insulating film disposed over the gate recess and the second semiconductor layer, a gate electrode disposed over the gate recess with the insulating film therebetween, and a source electrode and a drain electrode disposed over the first semiconductor layer or the second semiconductor layer, whereby a central portion of the gate recess is higher than a peripheral portion of the gate recess.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: March 1, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Endo, Toshihiro Ohki, Toshihide Kikkawa
  • Patent number: 9269782
    Abstract: A semiconductor device, comprising: a first semiconductor layer disposed on a substrate; a second semiconductor layer disposed on the first semiconductor layer; a lower insulating film disposed on the second semiconductor layer; a p-type electroconductive oxide film disposed on the lower insulating film; an upper insulating film disposed on the oxide film; and a gate electrode disposed on the upper insulating film, wherein the lower insulating film under the gate electrode has a depressed portion.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: February 23, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Masahito Kanamura, Toyoo Miyajima, Toshihiro Ohki
  • Patent number: 9257514
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: February 9, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
  • Patent number: 9209042
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: December 8, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20150279956
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Application
    Filed: June 9, 2015
    Publication date: October 1, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Patent number: 9123793
    Abstract: A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: September 1, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Hiroshi Endo
  • Patent number: 9099351
    Abstract: A compound semiconductor device includes as compound semiconductor layers: a first layer; a second layer larger in band gap than the first layer, formed above the first layer; a third layer having a p-type conductivity type, formed above the second layer; a gate electrode formed above the second layer via the third layer; a fourth layer larger in band gap than the second layer, formed to be in contact with the third layer above the second layer; and a fifth layer smaller in band gap than the fourth layer, formed to be in contact with the third layer above the fourth layer.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: August 4, 2015
    Assignee: Transphorm Japan, Inc.
    Inventors: Masato Nishimori, Tadahiro Imada, Toshihiro Ohki
  • Patent number: 9093512
    Abstract: A compound semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a source electrode and a drain electrode provided over the nitride semiconductor stacked structure; a gate electrode provided between the source electrode and the drain electrode, over the nitride semiconductor stacked structure; a field plate provided at least partially between the gate electrode and the drain electrode; and a plurality of insulation films and formed over the nitride semiconductor stacked structure, wherein a number of interfaces of the plurality of insulation films is smaller between the field plate and the drain electrode than in the vicinity of the gate electrode.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 28, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiro Ohki
  • Publication number: 20150194512
    Abstract: A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.
    Type: Application
    Filed: December 4, 2014
    Publication date: July 9, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, LEI ZHU, NAOYA OKAMOTO, Yuichi Minoura, Shirou OZAKI
  • Publication number: 20150194514
    Abstract: On a surface of a compound semiconductor layer including inner wall surfaces of an electrode trench, an etching residue 12a and an altered substance 12b which are produced due to dry etching for forming the electrode trench are removed, and a compound semiconductor is terminated with fluorine. Gate metal is buried in the electrode trench via a gate insulating film, or the gate metal is directly buried in the electrode trench, whereby a gate electrode is formed.
    Type: Application
    Filed: March 9, 2015
    Publication date: July 9, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Norikazu NAKAMURA, Toshihiro OHKI, Masahito KANAMURA
  • Patent number: 9035357
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima