Patents by Inventor Toshikazu Maekawa
Toshikazu Maekawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9405406Abstract: An image pickup device capable of stably detecting an object irrespective of use conditions while reducing manufacturing costs is provided. When illumination light from a backlight is emitted to a proximity object from an I/O display panel, an electric charge is accumulated in image pickup pixels in accordance with total light amount, including reflected light originating from the backlight and external environment light. Moreover, when the illumination light is not emitted, a discharging electric charge is released from the image pickup pixels in accordance with the amount of environment light. Thereby, an environment light component is subtracted from an image pickup signal obtained from each of the image pickup pixels, so object information about the proximity object is obtained without influence of the environment light. Moreover, in a light reception drive circuit, fewer frame memories for producing a picked-up image from the image pickup signal are necessary.Type: GrantFiled: May 6, 2015Date of Patent: August 2, 2016Assignee: Japan Display Inc.Inventors: Tsutomu Harada, Yoshiharu Nakajima, Michiru Senda, Kazunori Yamaguchi, Mitsuru Tateuchi, Ryoichi Tsuzaki, Toshikazu Maekawa
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Publication number: 20150301689Abstract: An image pickup device capable of stably detecting an object irrespective of use conditions while reducing manufacturing costs is provided. When illumination light from a backlight is emitted to a proximity object from an I/O display panel, an electric charge is accumulated in image pickup pixels in accordance with total light amount, including reflected light originating from the backlight and external environment light. Moreover, when the illumination light is not emitted, a discharging electric charge is released from the image pickup pixels in accordance with the amount of environment light. Thereby, an environment light component is subtracted from an image pickup signal obtained from each of the image pickup pixels, so object information about the proximity object is obtained without influence of the environment light. Moreover, in a light reception drive circuit, fewer frame memories for producing a picked-up image from the image pickup signal are necessary.Type: ApplicationFiled: May 6, 2015Publication date: October 22, 2015Inventors: Tsutomu Harada, Yoshiharu Nakajima, Michiru Senda, Kazunori Yamaguchi, Mitsuru Tateuchi, Ryoichi Tsuzaki, Toshikazu Maekawa
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Patent number: 9063613Abstract: An image pickup device capable of stably detecting an object irrespective of use conditions while reducing manufacturing costs is provided. When illumination light from a backlight 15 is emitted to a proximity object from an I/O display panel 20, an electric charge for charging is accumulated in each of image pickup pixels 33 in accordance with total light amount as a summation of reflected light Lon originating from the illumination light and environment light (outside light) L0. Moreover, when the above-described illumination light is not emitted, an electric charge for discharging is released from each of the image pickup pixels 33 in accordance with light amount of the environment light L0. Thereby, a component by the environment light L0 is subtracted in an image pickup signal obtained from each of the image pickup pixels 33, so object information about the proximity object is obtainable without influence of the environment light L0.Type: GrantFiled: March 18, 2009Date of Patent: June 23, 2015Assignee: Japan Display Inc.Inventors: Tsutomu Harada, Yoshiharu Nakajima, Michiru Senda, Kazunori Yamaguchi, Mitsuru Tateuchi, Ryoichi Tsuzaki, Toshikazu Maekawa
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Publication number: 20120162161Abstract: A liquid crystal display having: a liquid crystal display panel in which a plurality of pixels are two-dimensionally arranged at intersecting points of gate lines as many as a plurality of rows and signal lines as many as a plurality of columns which are wired in a matrix shape; and a plurality of driver ICs for applying a signal potential to each pixel of the liquid crystal display panel through the signal lines of a plurality of columns, wherein the number of output pins of each of a plurality of driver ICs is set to the measure of the total number of signal lines of a plurality of columns, thereby preventing that a fraction occurs in the signal lines.Type: ApplicationFiled: March 12, 2012Publication date: June 28, 2012Applicant: Sony CorporationInventors: Masumitsu Ino, Hiroyoshi Tsubota, Hiroaki Ichikawa, Shinichi Teraguchi, Taketo Oka, Toru Akutagawa, Toshikazu Maekawa, Yoshiharu Nakajima, Naoshi Goto
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Patent number: 8031188Abstract: A digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels.Type: GrantFiled: April 14, 2008Date of Patent: October 4, 2011Assignee: Sony CorporationInventors: Yoshiharu Nakajima, Toshikazu Maekawa
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Patent number: 7932901Abstract: A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.Type: GrantFiled: July 24, 2007Date of Patent: April 26, 2011Assignee: Sony CorporationInventors: Yoshitoshi Kida, Yoshiharu Nakajima, Toshikazu Maekawa
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Patent number: 7864170Abstract: A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side.Type: GrantFiled: April 23, 2007Date of Patent: January 4, 2011Assignee: Sony CorporationInventors: Yoshitoshi Kida, Yoshiharu Nakajima, Toshikazu Maekawa
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Patent number: 7796126Abstract: A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side.Type: GrantFiled: April 23, 2007Date of Patent: September 14, 2010Assignee: Sony CorporationInventors: Yoshitoshi Kida, Yoshiharu Nakajima, Toshikazu Maekawa
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Patent number: 7773084Abstract: In the present invention, during an 1H period excluding a blanking period (1HB) constituting a line display period, pixel data pulses of RGB (61B to 61R) are successively supplied for each color to corresponding signal lines for the color display of one pixel line. A control circuit (40) of select switches connected to the signal lines (6-1 to 6-n) supplies permission pulses (63B to 63R) for the supply of data to signal lines when displaying one color among RGB to select switches (TMG), and turns on the select switch (TMG) of the signal line corresponding to another color to be displayed later in the same line display period during the period of this application by a precharge pulse (62G or 62R) having a time duration shorter than the supply time of the pixel data of the other color (T2 or T3) to previously precharge the signal line of the other color to the predetermined potential.Type: GrantFiled: August 20, 2004Date of Patent: August 10, 2010Assignee: Sony CorporationInventors: Naoyuki Itakura, Hiroaki Ichikawa, Toshikazu Maekawa
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Publication number: 20100128004Abstract: An image pickup device capable of stably detecting an object irrespective of use conditions while reducing manufacturing costs is provided. When illumination light from a backlight 15 is emitted to a proximity object from an I/O display panel 20, an electric charge for charging is accumulated in each of image pickup pixels 33 in accordance with total light amount as a summation of reflected light Lon originating from the illumination light and environment light (outside light) L0. Moreover, when the above-described illumination light is not emitted, an electric charge for discharging is released from each of the image pickup pixels 33 in accordance with light amount of the environment light L0. Thereby, a component by the environment light L0 is subtracted in an image pickup signal obtained from each of the image pickup pixels 33, so object information about the proximity object is obtainable without influence of the environment light L0.Type: ApplicationFiled: March 18, 2009Publication date: May 27, 2010Applicant: Sony CorporationInventors: Tsutomu Harada, Yoshiharu Nakajima, Michiru Senda, Kazunori Yamaguchi, Mitsuru Tateuchi, Ryoichi Tsuzaki, Toshikazu Maekawa
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Patent number: 7432906Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.Type: GrantFiled: March 23, 2005Date of Patent: October 7, 2008Assignee: Sony CorporationInventors: Yoshiharu Nakajima, Yasuhito Maki, Toshikazu Maekawa
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Publication number: 20080224972Abstract: This invention relates to a digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels, a level shift circuit in the shift register has a basic structure of CMOS latch cells and is utilized in each level shift of the clock signal at each transfer stage, a sampling latch circuit with a basic structure of CMOS latch cells has a level shift function, and these respective circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated liquid crystal display device to provide an LCD panel with an extremely narrow picture frame, stable level shift operation, stable sampling & latType: ApplicationFiled: April 14, 2008Publication date: September 18, 2008Applicant: Sony CorporationInventors: Yoshiharu Nakajima, Toshikazu Maekawa
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Patent number: 7405720Abstract: An analog buffer circuit which has small input and output offsets and reduced power consumption even if it is formed on an insulating substrate by TFTs, a display device which uses the analog buffer circuit as a peripheral driving circuit for a display unit, and a portable terminal in which the display device is provided as a screen display unit are provided. By performing offset detection on a source follower in such a manner that, for example, two capacitors Cn1 and Cn2 are connected to the gate of a NMOS transistor Qn11 as a source follower, and conduction/nonconduction control of switches Sn1 to Sn5 are performed, if needed, and by sequentially canceling the detected offsets, a final offset voltage is sufficiently reduced and high precision offset cancellation is realized.Type: GrantFiled: May 30, 2003Date of Patent: July 29, 2008Assignee: Sony CorporationInventors: Yoshiharu Nakajima, Yoshitoshi Kida, Toshikazu Maekawa
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Patent number: 7400320Abstract: This invention relates to a digital/analog converter circuit, a level shift circuit, a shift-register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display (LCD) device. The LCD device includes an integrated drive circuit integrated and a digital/analog converter circuit. The digital/analog converter circuit has a matrix of polysilicon thin film transistors positioned on the substrate, as switching devices for the pixels. The shift register includes a level shift circuit and a sampling latch circuit These circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated LCD device to provide an LCD panel with a narrow picture frame, stable level shift operation, stable sampling & latch operation in a circuit having an extremely small number of components, low power consumption and a small surface area.Type: GrantFiled: December 15, 2003Date of Patent: July 15, 2008Assignee: Sony CorporationInventors: Yoshiharu Nakajima, Toshikazu Maekawa
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Publication number: 20080136810Abstract: In the present invention, during a 1H period excluding a blanking period (1HB) constituting a line display period, pixel data pulses of RGB (61B to 61R) are successively supplied for each color to corresponding signal lines for color display of one pixel line. A control circuit (40) of select switches connected to the signal lines (6-1 to 6-n) supplies permission pulses (63B to 63R) for supply of data to signal lines when displaying one color among RGB to select switches (TMG), and turns on the select switch (TMG) of the signal line corresponding to another color to be displayed later in the same line display period during the period of this application by a precharge pulse (62G or 62R) having a time duration shorter than the supply time of the pixel data of the other color (T2 or T3) to previously precharge the signal line of the other color to the predetermined potential.Type: ApplicationFiled: August 20, 2004Publication date: June 12, 2008Applicant: Sony CorporationInventors: Naoyuki Itakura, Hiroaki Ichikawa, Toshikazu Maekawa
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Patent number: 7368945Abstract: When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.Type: GrantFiled: May 26, 2006Date of Patent: May 6, 2008Assignee: Sony CorporationInventors: Yoshitoshi Kida, Yoshiharu Nakajima, Toshikazu Maekawa
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Publication number: 20070262975Abstract: A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.Type: ApplicationFiled: July 24, 2007Publication date: November 15, 2007Inventors: Yoshitoshi Kida, Yoshiharu Nakajima, Toshikazu Maekawa
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Publication number: 20070195038Abstract: A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side.Type: ApplicationFiled: April 23, 2007Publication date: August 23, 2007Inventors: Yoshitoshi Kida, Yoshiharu Nakajima, Toshikazu Maekawa
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Publication number: 20070195037Abstract: A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side.Type: ApplicationFiled: April 23, 2007Publication date: August 23, 2007Inventors: Yoshitoshi Kida, Yoshiharu Nakajima, Toshikazu Maekawa
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Patent number: 7250941Abstract: A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.Type: GrantFiled: May 6, 2003Date of Patent: July 31, 2007Assignee: Sony CorporationInventors: Yoshitoshi Kida, Yoshiharu Nakajima, Toshikazu Maekawa