Abstract: A D/A converter circuit according to the present invention allows adaptation to multi-gradation by reducing the circuit size. A reference-voltage-selection-type D/A converter circuit that converts 4-bit digital data into an analog signal having 16 voltage values V1 to V16 generates in a reference voltage generating circuit (11) four reference voltages Vref1 to Vref4 having four voltage values in time series and generates a selection signal in a selection signal generating circuit (12) based on low-order two bits of the digital data. A selection circuit (13) selects by time-sharing one of the four voltage values of each of the reference voltages Vref1 to Vref4 based on this selection signal and outputs the analog signal of the selected voltage value to an output line (15).

Abstract: A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side.

Abstract: In the case of an active matrix type TFT liquid crystal display apparatus of a dot successive driving system, between respectives of signal lines sig1A through sig4A wired at respective columns, and respectives of a signal line 18-1A for inputting a precharge signal Psig-black at a black level and a precharge signal line 18-2A for inputting a precharge signal Psig-gray at a gray level, sampling switches Pb1A through Pb4A and Pg1A through Pg4A of two routes are connected, to respectives of the signals lines sig1A through sig4A, firstly, the precharge signal Psig-black, successively, the precharge signal Psig-gray at the gray level are written in this order and thereafter, an image signal video is written thereto.

Abstract: When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.

Abstract: When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.

Abstract: The present invention is directed to a liquid crystal display panel to which an external horizontal drive circuit is connected in a TAB, COG, or other form. The liquid crystal display panel is capable of performing aging by a substrate alone by connecting the external drive circuit. The liquid crystal display panel includes an active matrix display area, a vertical drive circuit, and a horizontal aging circuit that supplies signals to a plurality of source lines at one time provided on a substrate. The medium-sized to small-sized active matrix type liquid crystal display apparatus is used in a PDA applications, among other, and is capable of being produced at a high quality and a low cost without using a time sharing driving method. The active matrix type liquid crystal display apparatus is provided with a horizontal drive circuit as an external circuit, wherein a vertical drive circuit is formed integrally with a liquid crystal display area on a glass substrate by using low temperature PolySi TFTs.

Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.

Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.

Abstract: A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side.

Abstract: An analog buffer circuit which has small input and output offsets and reduced power consumption even if it is formed on an insulating substrate by TFTs, a display device which uses the analog buffer circuit as a peripheral driving circuit for a display unit, and a portable terminal in which the display device is provided as a screen display unit are provided. By performing offset detection on a source follower in such a manner that, for example, two capacitors Cn1 and Cn2 are connected to the gate of a NMOS transistor Qn11 as a source follower, and conduction/nonconduction control of switches Sn1 to Sn5 are performed, if needed, and by sequentially canceling the detected offsets, a final offset voltage is sufficiently reduced and high precision offset cancellation is realized.

Abstract: An active-matrix-type liquid crystal display device supplies signal potentials to signal lines of a liquid crystal display panel according to a time-division drive method using time-division switches. The low-level potential of select pulses to be supplied from a select pulse generating circuit to CMOS analog switches of the time-division switches is set to be lower than the low-level potential of a signal potential output from a horizontal drive circuit. With this arrangement, even if the signal potential of a non-selected signal line is decreased due to the crosstalk of a signal potential from a selected signal line to the non-selected signal line, the generation of insufficient contrast and non-uniformity of the luminance in the horizontal direction can be prevented. As a consequence, a high image quality is maintained.

Abstract: This invention provides a liquid crystal display device having a partial screen display mode, in which a latch control circuit (17) first stores white data or black data as color data of one line to latch circuits (121), (131) at the beginning of an image non-display period and then repeatedly reads out and outputs the color data to respective column lines in a display area (11) until the display period ends, thereby stopping the operation to write data to the latch circuits (121), (131) substantially during the entire image non-display period.

Abstract: When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.

Abstract: A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.

Abstract: This invention relates to a digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels, a level shift circuit in the shift register has a basic structure of CMOS latch cells and is utilized in each level shift of the clock signal at each transfer stage, a sampling latch circuit with a basic structure of CMOS latch cells has a level shift function, and these respective circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated liquid crystal display device to provide an LCD panel with an extremely narrow picture frame, stable level shift operation, stable sampling & lat

Abstract: A laser annealing apparatus for fabricating a thin film semiconductor device integratedly formed with thin film transistors each of which includes a semiconducting thin film formed on the surface of an insulating substrate spread in longitudinal and lateral directions and then crystallized. A band-shaped pulsed laser beam irradiates the insulating substrate along the longitudinal direction. The laser beam is simultaneously moved in the lateral direction with a specific movement pitch while partially overlapping regions irradiated with the laser beam. The movement pitch of the laser beam is set at a value equal to an arrangement pitch of the thin film transistors or at a value larger by a factor of an integer than the arrangement pitch. The insulating substrate is previously positioned such that the boundaries of the partially overlapped irradiated regions are not overlapped on a channel region of any of the thin film transistors.

Abstract: A D/A converter circuit according to the present invention allows adaptation to multi-gradation by reducing the circuit size. A reference-voltage-selection-type D/A converter circuit that converts 4-bit digital data into an analog signal having 16 voltage values V1 to V16 generates in a reference voltage generating circuit (11) four reference voltages Vref1 to Vref4 having four voltage values in time series and generates a selection signal in a selection signal generating circuit (12) based on low-order two bits of the digital data. A selection circuit (13) selects by time-sharing one of the four voltage values of each of the reference voltages Vref1 to Vref4 based on this selection signal and outputs the analog signal of the selected voltage value to an output line (15).

Abstract: This invention relates to a digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels, a level shift circuit in the shift register has a basic structure of CMOS latch cells and is utilized in each level shift of the clock signal at each transfer stage, a sampling latch circuit with a basic structure of CMOS latch cells has a level shift function, and these respective circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated liquid crystal display device to provide an LCD panel with an extremely narrow picture frame, stable level shift operation, stable sampling & lat

Abstract: To readily realize a reduction in pel pitch and an increase in the number of pels, a V shift register is configured such that one pulse transfer stage is provided so as to correspond to two horizontal pel lines constituting a pel section of a liquid crystal panel. Further, a decoder decodes a signal output from each pulse transfer stage of the V shift register, thereby preparing a gate pulse for individually driving the pel line. The number of pulse transfer stages is made half that of a conventional pel drive circuit.

Abstract: A process of fabricating a thin film semiconductor device includes the steps of: forming a semiconducting thin film on an insulating substrate; annealing the semiconducting thin film by irradiating a laser beam thereon, thereby crystallizing the semiconducting thin film; and integratedly forming thin film transistors, each including the semiconducting thin film as an active layer, with a specific arrangement pitch. In the laser annealing step, a pulsed laser beam formed in a band-shape is intermittently irradiated onto the insulating substrate and it is simultaneously moved relative to the insulating substrate in the lateral direction with a specific movement pitch to form partially overlapping regions irradiated with the laser beam between the irradiated regions.