Abstract: In a liquid crystal display device, sampling means and gate circuits are provided at every signal line, whereby a load in the sampling operation is reduced to carry out the sampling operation with ease. Simultaneously, the charge supplying time to the signal lines can be extended to thereby charge the signal lines by the signals satisfactorily. Thus, the quality of a displayed image can be prevented from being deteriorated.

Abstract: A horizontal driver circuit comprising a shift register for generating horizontal sampling pulses sequentially; and a fixed pattern eliminating circuit, associated with the shift register, for providing a non-overlap time of the horizontal sampling pulses between an Nth stage and an Mth stage posterior thereto. The Mth stage horizontal sampling pulse has a rise whose phase is the same as that of a fall of the Nth stage horizontal sampling pulse. The fixed pattern eliminating circuit comprises means for controlling the rise of the horizontal sampling pulse of the Mth stage by the fall of the horizontal sampling pulse of the Nth stage. The horizontal driver circuit is applicable to a two-dimensional addressing device and a liquid crystal display device to eliminate a fault of vertical streaks on a displayed image.

Abstract: To restrict a potential oscillation in a video line caused by a high speed sampling rate, the active matrix display device is comprised of gate lines X in row, signal lines Y in column and liquid crystal pixels LC of matrix arranged at each of the crossing points of both lines. The V driver 1 scans in sequence each of the gate lines X and selects the liquid crystal pixels LC in one line for every one horizontal period. The H driver 4 performs a sampling of the video signal VSIG for each of the signal lines Y and performs a writing of the video signal VSIG in the liquid crystal pixels LC in one selected line within one horizontal period. The precharging means 5 supplies the predetermined precharging signal VPS to each of the signal lines Y just before writing the video signal VSIG for the liquid crystal pixels LC in one line.

Abstract: A level converting circuit for an input clock signal having a relatively low amplitude comprising a level converting circuit for converting the input clock signal to an output clock signal having a relatively high amplitude, the level converting circuit having an input transistor which has a predetermined threshold voltage, and detecting/offsetting circuit for detecting the threshold voltage of the input transistor and adding an offset voltage in response to the detected threshold voltage to the input clock signal and then for providing the offset input clock signal to the level converting circuit. The novel setup performs clock interfacing of a thin-film transistor integrated circuit device represented by an active-matrix liquid crystal display device at a relatively high speed at a low voltage below 3 V for example.

Abstract: An active matrix display device comprises a plurality of pixels, a vertical scanning circuit, a horizontal addressing circuit, a wide input switch element and a normal input switch element. The plurality of pixels are arrayed in a matrix shape. The vertical scanning circuit sequentially selects pixels every line. The horizontal addressing circuit dot-sequentially addresses selected line pixels and has a shift register constituted by a number of multi-stage connected flip-flops, the number of which corresponds to the total number of rows of pixels. Each flip-flop is equipped with a pair of input/output terminals and a prescribed start pulse is transferred every stage. The wide input switch element inputs a start pulse to an input terminal of a flip-flop positioned at a leading stage during wide displaying. The normal input switch element inputs a start pulse to an input of a flip-flop positioned at a specific intermediate stage during normal displaying.

Abstract: To restrict a potential oscillation in a video line caused by a high speed sampling rate, the active matrix display device is comprised of gate lines X in row, signal lines Y in column and liquid crystal pixels LC of matrix arranged at each of the crossing points of both lines. The V driver 1 scans in line sequence each of the gate lines X and selects the liquid crystal pixels LC in one line for every one horizontal period. The H driver 2 performs in sequence samplings of the video signal VSIG within one horizontal scanning period to each of the signal lines Y and performs a writing of the video signal VSIG by dot sequential scanning to the liquid crystal pixels LC in one selected line. The precharging means 4 supplies in sequence the predetermined precharging signal VPS prior to the sequential sampling of the video signal VSIG for each of the signal lines Y.

Abstract: A level converting circuit for an input clock signal having a relatively low amplitude comprising a level converting circuit for converting the input clock signal to an output clock signal having a relatively high amplitude, the level converting circuit having an input transistor which has a predetermined threshold voltage, and detecting/offsetting circuit for detecting the threshold voltage of the input transistor and adding an offset voltage in response to the detected threshold voltage to the input clock signal and then for providing the offset input clock signal to the level converting circuit. The novel setup performs clock interfacing of a thin-film transistor integrated circuit device represented by an active-matrix liquid crystal display device at a relatively high speed at a low voltage below 3 V for example.

Abstract: An active matrix display device is disclosed which realizes changing over between a wide display and a normal display with a simple construction. The active matrix display device includes picture elements disposed in rows and columns on a horizontally elongated screen. A gate line is connected to each picture element row, while a data line is connected to each picture element column. A signal line for supplying a video signal and data lines are connected by way of sampling switches. A horizontal shift register controls sequential opening and closing operations of the sampling switches. The picture element columns of the horizontally elongated screen are divided into a predetermined area allocated to a normal display and a pair of expansion areas included in a wide display. The horizontal shift register is divided into a predetermined stage section corresponding to the predetermined area and expansion stage sections corresponding to the expansion areas.

Abstract: A liquid crystal display device of the active matrix type which prevents residual of charge in liquid crystal picture elements with respect to time. The active matrix liquid crystal display device includes liquid crystal picture elements formed from a liquid crystal layer held between picture element electrodes arranged in a matrix and common electrodes opposing to the picture element electrodes, and picture element transistors corresponding to the liquid crystal picture elements. While a predetermined reference potential is supplied to the common electrode, image signals are applied to the individual picture element electrodes by way of signal lines and picture element transistors to effect ac driving of the liquid crystal picture elements.

Abstract: A method for manufacturing an active matrix array substrate having a plurality of pixel drive cells, each pixel drive cell includes a pixel switching element and a capacitor element connected to the pixel switching element in series. The method comprising the inspection steps of storing a charge in the capacitor element and detecting the charge stored in the capacitor element by measuring the voltage and comparing the voltage measured with a reference voltage obtained with a good pixel.

Abstract: An output buffer circuit is disclosed in which a first signal whose voltage amplitude is smaller than the voltage between zero and the power source voltage VDD and the minimum level is the same as the ground level Gnd and a second signal whose maximum level is the same as the power source voltage VDD but the voltage amplitude is smaller than the voltage between zero and the power source voltage VDD are generated, and it is thereby arranged such that maximum value of the voltages applied between any two terminals of all of the MOS transistors constituting the output buffer circuit becomes .vertline.VDD-threshold voltage of MOS transistor.vertline.. Therefore, the withstand voltage of devices can be substantially improved. In addition, depending on the first and second signals, the finally output signal can be given the amplitude between the ground level Gnd and the power source voltage VDD.

Abstract: A level converting circuit for converting input signals into different level signals which enables a stable high speed operation to be realized and which may be used advantageously for driving, above all, liquid crystal display devices. Voltage clamping circuits 1 and 2 are provided at signal input terminals of n-MOS transistors 3 and 4 connected to the drains of pMOS transistors 5 and 6 connected in a current mirror configuration. By these voltage clamping circuits 1 and 2, the input levels of the nMOS transistors 3 and 4 are shifted to higher levels, as a result of which a current larger than that in the conventional circuit flows through the nMOS transistors 3 and 4 to speed up charging and discharging. Stable driving may be enabled even when the nMOS transistors 3 and 4 are formed as thin film field effect transistors for use with liquid crystal display elements.

Abstract: In a liquid crystal display device, sampling means and gate circuits are provided at every signal line, whereby a load in the sampling operation is reduced to carry out the sampling operation with ease. Simultaneously, the charge supplying time to the signal lines can be extended to thereby charge the signal lines by the signals satisfactorily. Thus, the quality of a displayed image can be prevented from being deteriorated.

Abstract: A thin film MOS transistor has a construction which can minimize scattering of electron and thus maximize electrons mobility for allowing higher speed operation of the transistor. For this, the MOS transistor has a thin film semiconductor layer having a thickness in a range less than or equal to 100 nm, between a pair of gate electrodes which oppose each other across the semiconductor layer.

Abstract: A shift register apparatus comprising unit registers, clocks and gates. Only when data input to the apparatus is significant enough to shift the state of the unit registers, is the clock signal supplied selectively to the unit register of the applicable stage. The selective supplying of the clock signal reduces the power fed to clock lines. With a larger number of shift stages, a greater amount of power will be saved, especially in applications where the apparatus is used to generate multiphase pulses. Fewer drivers are needed to drive the clock signal, which may be supplied at the TTL level.

Abstract: A photosensor has a PIN photodiode and a piling-type capacitor is connected in parallel with the PIN photodiode so as to increase the reverse bias capacitance of the PIN photodiode so as to increase the dynamic range.

Abstract: A solid state image pickup device comprises first switching elements (S'.sub.11 to S'.sub.mn) arrayed in horizontal and vertical rows and composed of a plurality of P-channel insulated-gate field-effect transistors, the first switching elements in each vertical row having one terminals connected in common, a photoelectric transducer layer (17) disposed over the horizontal and vertical rows of the first switching elements (S'.sub.11 to S'.sub.mn) and electrically connected to other terminals of the first switching elements (S'.sub.11 to S'.sub.mn), and a plurality of second switching elements (T.sub.1 to T.sub.n) disposed respectively for the vertical rows of the first switching elements (S'.sub.11 to S'.sub.mn) and connected respectively to the one terminals connected in common of the first switching elements in the respective vertical rows, with the arrangement thereof wherein the horizontal rows of the first switching elements (S'.sub.11 to S'.sub.

Abstract: A solid state image pickup device comprises a plurality of image pickup picture units (E.sub.11 to E.sub.mn) arrayed in horizontal and vertical rows and composed of first switching elements (S.sub.11 to S.sub.mn) and photoelectric transducers (D.sub.11 to D.sub.mn : 24) electrically connected to the first switching elements (S.sub.11 to S.sub.mn), and a plurality of second switching elements (T'.sub.1 to T'.sub.n) connected in common to the respective vertical rows of the first switching elements (S.sub.11 to S.sub.mn) in the image pickup picture units (E.sub.11 to E.sub.mn) and each composed of a depletion-mode insulated-gate field-effect transistors. The horizontal rows of the first switching elements (S.sub.11 to S.sub.mn) in the image pickup picture units (E.sub.11 to E.sub.mn) are selectively energizable and the second switching elements (T'.sub.1 to T'.sub.n) are also selectively energizable to deliver signals based on signal charge generated by the photoelectric transducers (D.sub.11 to D.sub.

Abstract: A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage.

Abstract: In a solid state image pickup apparatus comprising a solid state image pickup device (1) which has an image pickup surface composed of a plurality of image pickup picture units (E.sub.11 -E.sub.mn), each of which contains a first switching element (S.sub.11, S.sub.12, . . . S.sub.mn) and a photoelectric converter (D.sub.11, D.sub.12, . . . D.sub.mn) electrically connected to the first switching element, and which are disposed in a predetermined arrangement and second switching elements (T.sub.1 -T.sub.n) connected to the image pickup picture units (E.sub.11 -E.sub.mn) and vertical and horizontal scanning circuits (13:14) for driving the first and second switching elements (S.sub.11 -S.sub.mn :T.sub.1 -T.sub.n), the vertical and horizontal scanning circuits (13:14) are made operative in a stable state to cause the first and second switching elements (S.sub.11 -S.sub.mn :T.sub.1 -T.sub.