Abstract: A power generator circuit, generation method, and liquid crystal display (LCD) wherein the power generator circuit does not require the design of a set when a negative or positive power generator circuit is installed outside the LCD panel. In a liquid crystal display integrated-with-drive circuit, a positive or negative power generator circuit is incorporated into the LCD panel and supplies a positive or negative voltage to a vertical driver circuit.

Abstract: In the case of an active matrix type TFT liquid crystal display apparatus of a dot successive driving system, between respectives of signal lines sig1A through sig4A wired at respective columns, and respectives of a signal line 18-1A for inputting a precharge signal Psig-black at a black level and a precharge signal line 18-2A for inputting a precharge signal Psig-gray at a gray level, sampling switches Pb1A through Pb4A and Pg1A through Pg4A of two routes are connected, to respectives of the signals lines sig1A through sig4A, firstly, the precharge signal Psig-black, successively, the precharge signal Psig-gray at the gray level are written in this order and thereafter, an image signal video is written thereto.

Abstract: First aspect of the present invention: In dot inversion driving, polarities of image signals written to contiguous left and right ones of pixels differ from each other and accordingly, a domain is produced at corners of an opening portion, as a result, an aperture rate of the pixel is lowered and the transmittivity is deteriorated. In the case of an active matrix type TFT liquid crystal display apparatus of a dot successive driving system, gate lines Vg1 through Vg5 are wired to meander between the pixels of two upper and lower lines, Cs lines are wired in a matrix shape, image signals video1 and video2 having polarities inverse to each other are simultaneously written to the pixels of different upper and lower two lines and polarities of the pixels in a pixel arrangement after the writing operation are made the same polarity between contiguous left and right ones of the pixels and inverse polarities between upper and lower ones of the pixels.

Abstract: A power generator circuit, generation method, and liquid crystal display (LCD) wherein the power generator circuit does not require the design of a set when a negative or positive power generator circuit is installed outside the LCD panel. In a liquid crystal display integrated-with-drive circuit, a positive or negative power generator circuit is incorporated into the LCD panel and supplies a positive or negative voltage to a vertical driver circuit.

Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.

Abstract: In a reference-voltage-selection-type D/A converter, the channel widths of transistors of MOS switches of gradation selecting units are weighted depending on the selected gradation. Specifically, the channel width of the MOS switches Qn11, Qn12 is represented by W0, the channel width of the MOS switches Qn13, Qp11 is represented by W1, the channel width of the MOS switches Qp12, Qn14 is represented by W2, and the channel width of the MOS switches Qp13, Qp14 is represented by W3. The channel width W3 is set to a size corresponding to the maximum capacitance of a column line, and the other channel widths W0, W1, W2 are set to satisfy the relationship: W0<W1<W2<W3. With this arrangement, the frame of a display panel which incorporates the D/A converter is reduced in size.

Abstract: This invention provides a liquid crystal display device having a partial screen display mode, in which a latch control circuit (17) first stores white data or black data as color data of one line to latch circuits (121), (131) at the beginning of an image non-display period and then repeatedly reads out and outputs the color data to respective column lines in a display area (11) until the display period ends, thereby stopping the operation to write data to the latch circuits (121), (131) substantially during the entire image non-display period.

Abstract: When time-division driving, which allows the number of output pins of a driver IC to be reduced, is applied to an active-matrix LCD apparatus, a time-division number is set to an odd number, preferably to the n-th (n: natural number) power of three, and a time-sequential signal (dot inversion signal) output from the driver IC is time-divided by a time-division switch and sent to signal lines 12-1, 12-2, 12-3, . . . to implement complete dot inversion driving.

Abstract: An output buffer is composed of first and second CMOS inverters that are connected to each other in cascade, a level conversion circuit for converting the low-voltage-side potential of output voltages of the first and second CMOS inverters to a potential that is lower than the low-voltage-side potential, and a third CMOS inverter provided downstream of the level conversion circuit. Since the level conversion circuit has a current mirror circuit configuration, the power consumption in the level conversion circuit is made small.

Abstract: An active-matrix display device includes rows of gate lines, columns of signal lines, and a matrix of liquid-crystal pixels provided in the region where the gate lines and the signal lines intersect. Vertical scanners sequentially scan each gate line during one vertical period, and select one row of liquid-crystal pixels. A horizontal scanner samples video signal for each signal line, and writes the video signal in the one row of liquid-crystal pixels selected within one horizontal period. A voltage applying means applies to each signal line a voltage equal to or less than the minimum level of the video signal in one horizontal period excluding a time assigned for writing the video signal in one row of liquid-crystal pixels. The repeated application of the voltage during one vertical period approximately equalizes signal leakages from all the pixels, whereby vertical crosstalk can be suppressed.

Abstract: In a source follower circuit having an NMOS source follower transistor with a drain thereof connected to a power supply and a current supply connected across the source of this transistor and earth, one end of a capacitor is connected to the gate of the transistor, the first analog switch is connected across the gate of the transistor and a precharge supply, the second analog switch is connected across the other end of the capacitor and the source of the transistor, and the third analog switch is connected across the other end of the capacitor and a signal source.

Abstract: A data latch circuit of a liquid crystal display device digital input data is converted into data of a power supply voltage level by comparing it with a comparison reference voltage in a comparator section having a PMOS differential amplifier circuit in a sampling period of a sampling pulse signal. The converted data is latched by a first data latch section in a non-sampling period of the sampling pulse signal. The latched data is held for a 1H period by a second data latch section.

Abstract: An active-matrix display device includes rows of gate lines, columns of signal lines, and a matrix of liquid-crystal pixels provided in the region where the gate lines and the signal lines intersect. Vertical scanners sequentially scan each gate line during one vertical period, and select one row of liquid-crystal pixels. A horizontal scanner samples video signal for each signal line, and writes the video signal in the one row of liquid-crystal pixels selected within one horizontal period. A voltage applying means applies to each signal line a voltage equal to or less than the minimum level of the video signal in one horizontal period excluding a time assigned for writing the video signal in one row of liquid-crystal pixels. The repeated application of the voltage during one vertical period approximately equalizes signal leakages from all the pixels, whereby vertical crosstalk can be suppressed.

Abstract: A driving circuit combined type LCD which employs sampling system of analog video signals can not be applied to a medium to large sized LCD. To solve this problem, in an active matrix type LCD having a driving circuit unit which is capable of accepting digital signals having the signal level lower than the power source voltage of a horizontal driving circuit system and pixel unit formed combinedly, level shift circuits for converting the level of sampled digital signals having a small amplitude to digital signals having a voltage of 0 to the power source voltage Vd (for example, 12 V) are provided between sampling switches and latch circuits, thus the structure is capable of accepting digital signals having a small signal amplitude from the outside.

Abstract: A liquid crystal display device having output buffers corresponding to column lines, and comprising analog switches provided between output ends of the output buffers and the column lines respectively, and a switch controller for on-off controlling the analog switches. A DA converter is provided in the preceding stage of the output buffers, and the switch controller turns off the analog switches during a DA conversion period of the DA converter or during a precharge period prior to DA conversion, and turns on the analog switches during a predetermined period other than such periods. The output buffers are disconnected from or connected to the column lines when the analog switches are turned off or turned on.

Abstract: Since each driving circuit has corresponded to the entire range of signal voltage, the dynamic range is large, it is difficult to constitute it by high Vth transistors, and a circuit having sufficient driving capacity for both input and output of current must be used, leading to increased circuit area and current consumption. To solve the problem, a circuit for driving column lines is divided into two in response to signal voltage with, for example, the common voltage as a reference, and these two column line driving circuits are arranged on the upper and lower sides of the LCD effective screen portion every two columns, and when the output end of the one column line driving circuit is connected to one of two column lines the analog switches are open-close timing controlled so that the output end of the other column line driving circuit is connected to the other of the two column lines.

Abstract: An active matrix display device comprising row gate lines, column signal lines and matrix pixels disposed at intersections of the gate and signal lines. The display device also includes a V shift register for line-sequentially scanning the gate lines and selecting pixels of one row during each horizontal scanning period, and a horizontal scanning circuit for sequentially sampling an actual video signal to the signal lines within one horizontal scanning period and writing the sampled actual video signal dot-sequentially in the pixels of one row. A precharge means is included as a characteristic requisite, wherein a first precharge signal is supplied simultaneously to the entire signal lines during a blanking period which precedes the horizontal scanning period, and further a second precharge signal is supplied sequentially to the signal lines prior to the step of sequentially sampling the actual video signal to the signal lines during each horizontal scanning period.

Abstract: The invention provide a display apparatus of a plural pixel simultaneous driving system wherein sample and hold noise included in a video signal is removed before the video signal is supplied to a display panel. A video signal processing circuit operates in response to a timing signal supplied from an external timing signal source, and delays an input video signal supplied thereto from an external video signal source to produce an output video signal. The video signal processing circuit includes a first sample and hold circuit, a second sample and hold circuit and a differential circuit. The first sample and hold circuit repetitively samples and holds the input video signal in response to the timing signal. The second sample and hold circuit repetitively samples and holds a predetermined reference signal in response to the same timing signal.

Abstract: A semiconductor device includes an insulating substrate; a plurality of pixel electrodes arranged in a matrix on the insulating substrate; first thin film transistors for individually driving the pixel electrodes; and driving circuits composed of second thin film transistors formed on the insulating substrate. In this semiconductor device, each of the first and second thin film transistors has a bottom-gate structure comprising a gate electrode patterned on the insulating substrate; a gate insulating film covering the gate electrode; and a semiconducting thin film having a channel region and a source/drain region, which is formed on the gate insulating film. Each of the second thin film transistors has a lightly doped region at least between a drain side highly doped region and the channel region.

Abstract: A bidirectional signal transfer shift register with a simple circuit construction is disclosed together with suitable applications of the same. The bidirectional signal transfer shift register comprises a plurality of flipflops each having an input terminal and an output terminal in pair. The input and output terminals of the flipflops are connected successively in such a manner as to construct a multi-stage structure. A forward route gate element is interposed in a connection route between the output terminal of the front stage side one of each two adjacent front and rear ones of the flipflops and the input terminal of the rear stage side flipflop, and a reverse route gate element is interposed in another connection route between the output terminal of the rear stage side flipflop and the input terminal of the front stage side flipflop.