Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Abstract: In order to produce a cellulose ester film constructed of a front layer, an intermittent layer and a rear layer, a dope solution is doped on a supporter. In at least one of the front layer and the rear layer, a mass ratio of a cotton linter to a wood pulp (cotton linter/wood pulp) is between 5/95 and 0/100, and a solvent of the dope contains more than 15 wt. % alcohols and hydrocarbons whose carbon number each is 1-10. Further, a ratio of a solid content density of a solution for forming the front layer and the rear layer to a solid density of a solution for forming the intermittent layer is less than 0.9 wt. %, and a total thickness of the solutions for front and rear layers is more than 5% of the dope ribbon.

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Abstract: A synchronous dynamic memory has a clock input buffer receiving an external clock and outputting an input external clock, a command input buffer receiving commands, an address input buffer receiving addresses, and a data input buffer receiving data. During normal operation mode, the clock input buffer supplies the clock to the command, address, and data input buffers. During data hold modes, such as power down mode, the clock input buffer supplies the clock to the command input buffer but not to the address and data input buffers.

Abstract: A positive thermistor element is supported by being clamped by first and second resilient contact members that are opposed to each other so as to be disposed along a diagonal and first and second positioning protrusions that are opposed to each other so as to be disposed along the other diagonal of the positive thermistor element. The first resilient contact member is located toward the periphery of the positive thermistor element from the second positioning protrusion and the second resilient contact member is positioned toward an inner portion of the positive thermistor element from the first positioning protrusion.

Abstract: A semiconductor memory device, comprising a fuse circuit which indicates a defective portion in a row direction, and also indicates the defective portion in a column direction, and a control circuit which switches data buses to avoid the defective portion indicated in the column direction by the fuse circuit when the defective portion indicated in the row direction by the fuse circuit corresponds to a row address that is input to the semiconductor memory device.

Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Abstract: A film is formed by casting a ribbon on a support from a flow cast die while pulling said ribbon toward said support by providing a decompression area. The decompression area is divided into a middle portion, a left portion and a right portion.

Abstract: In the transparent film of optical application or the support for photographic material produced by a solution film forming method, the polymer resin film on which any coating unevenness does not occur even when a functional layer is coated on the film surface and the manufacturing method for the film are proposed.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: This invention relates to a solution casting process capable of decreasing uneven coating of a functional layer upon applying the functional layer onto a film surface, which comprises casting a solution of polymer dissolved in organic solvent into a film by extruding from a die onto a support, wherein the length of the film from the die opening to the landing of the film on the support is controlled to 3 to 40 mm.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: The present invention relates to a therapeutic agent for cartilaginous diseases, an accelerator for chondrocyte proliferation and an accelerator for proteoglycan production comprising HGF (hepatocyte growth factor) as an active component, and a treatment method for cartilaginous diseases of human or mammals comprising administering an effective amount of HGF. The active component HGF has an effect to promote the proliferation of chondrocytes and to promote the production of proteoglycan. Therefore, the therapeutic agent and accelerator of the present invention are useful for the prevention and treatment of various disorders caused by cartilaginous diseases.

Abstract: The invention relates to an anti-cancer agent containing &agr;-chain protein (&agr;-fragment) of HGF (hepatocyte growth factor) as an active ingredient. The active ingredient of &agr;-fragment has a specific suppressing effect on invasion and metastasis of cancer cells such as gallbladder cancer, lung cancer and other, which are highly metastatic and result in a high mortality. Therefore, the agent of the invention is used in treatment and prevention of cancer as an anti-cancer agent, and is extremely useful clinically.

Abstract: A positive thermistor element is supported by being clamped by first and second resilient contact members that are opposed to each other so as to be disposed along a diagonal and first and second positioning protrusions that are opposed to each other so as to be disposed along the other diagonal of the positive thermistor element. The first resilient contact member is located toward the periphery of the positive thermistor element from the second positioning protrusion and the second resilient contact member is positioned toward an inner portion of the positive thermistor element from the first positioning protrusion.

Abstract: The present invention relates to a method for treating fibrosis caused by excessive collagen deposition. The method involves administering Hepatocyte Growth Factors (HGFs). The HGFs accelerate the decomposition of the collagen when administered in an effective amount.

Abstract: An electronic part in which insulating tape is adhered to lead terminals which extend from an electronic part unit so that a pitch between the terminals can remain stable and constant. The insulating tape is adhered to portions of the lead terminals in a vicinity of the unit from both sides such that the tape is placed with the terminals therebetween.

Abstract: According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.

Abstract: The present invention relates to a medicament comprising a HGF gene. The medicament of the present invention may be topically applied to the target organs so that the effects can be selectively exhibited, resulting in minimizing the side effects of HGF.

Abstract: A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.