Patents by Inventor Toshikazu Nakamura

Toshikazu Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6756358
    Abstract: The present invention relates to a therapeutic agent for cartilaginous diseases, an accelerator for chondrocyte proliferation and an accelerator for proteoglycan production comprising HGF (hepatocyte growth factor) as an active component, and a treatment method for cartilaginous diseases of human or mammals comprising administering an effective amount of HGF. The active component HGF has an effect to promote the proliferation of chondrocytes and to promote the production of proteoglycan. Therefore, the therapeutic agent and accelerator of the present invention are useful for the prevention and treatment of various disorders caused by cartilaginous diseases.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: June 29, 2004
    Assignee: Sumitomo Pharmaceuticals Co., Ltd.
    Inventors: Masahiro Iwamoto, Sumihare Noji, Toshikazu Nakamura
  • Publication number: 20040105882
    Abstract: The present invention relates to a medicament comprising a HGF gene. The medicament of the present invention may be topically applied to the target organs so that the effects can be selectively exhibited, resulting in minimizing the side effects of HGF.
    Type: Application
    Filed: July 9, 2003
    Publication date: June 3, 2004
    Applicant: MedGene Bioscience, Inc.
    Inventors: Ryuichi Morishita, Toshio Ogihara, Toshikazu Nakamura, Tetsuya Tomita, Takahiro Ochi
  • Publication number: 20040090846
    Abstract: A semiconductor memory with a memory core for dynamically holding data in which a data collision at the time of the semiconductor memory making the transition from a standby state to a nonstandby state is prevented. A first buffer circuit inputs an enable signal for controlling a standby state or a nonstandby state. A second buffer circuit outputs a predetermined logic signal or a read/write signal for controlling the reading of data from or the writing of data to the memory core in accordance with the enable signal. A third buffer circuit outputs an inverted signal obtained by inverting the logic signal or the read/write signal in accordance with the enable signal. A control circuit controls the reading or writing of the data by the read/write signal outputted from the second buffer circuit. A data output control circuit controls the inputting of the data from or the outputting of the data to the outside by the inverted signal or the read/write signal outputted from the third buffer circuit.
    Type: Application
    Filed: November 3, 2003
    Publication date: May 13, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi Eto, Toshikazu Nakamura, Toshiya Miyo
  • Publication number: 20040058179
    Abstract: The dope prepared from a mixture solvent and solid contents such as cellulose ester and additives is cast on a drum cooled to −5° C. to form a gel-like film. The gel-like film is peeled off from the drum. Tension of 60 kg/m is applied to the gel-like film in the widthwise direction thereof and the temperature of the gel-like film is kept 120° C., when the content of the solvent to the solid contents in the gel-like film is in a range of 100 wt. % to 20 wt. %. Further the gel-like film is dried to be a cellulose ester film having 40 &mgr;m thickness. The IR spectrum of the cellulose ester film has a peak in a range of 520 cm−1 to 480 cm−1 which indicates the crystallization of the polymer. The cellulose ester film has tear strength of 12 g, Rth of 42 nm and Re of 1.2 nm. As crystallization of the polymer proceeds, the cellulose ester film has sufficient strength and optical properties.
    Type: Application
    Filed: September 17, 2003
    Publication date: March 25, 2004
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventors: Hidekazu Yamazaki, Toshikazu Nakamura, Hiroshi Miyachi
  • Patent number: 6699837
    Abstract: The invention relates to a therapeutic agent for disorder in brain and nerve containing HGF (hepatocyte growth factor) as an active ingredient, and a method for treatment of disorder in brain and nerve comprising administration of HGF. The active ingredient HGF possesses an action to prolong survival of brain and nerve cells, and the injured brain or nerves may be regenerated and restored. Therefore, the therapeutic agent and method for treatment of the invention are useful for prevention and treatment of various disorder in brain and nerve (for example, dementia, senile dementia of Alzheimer type, cerebral stroke, and cerebral infarction).
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: March 2, 2004
    Inventor: Toshikazu Nakamura
  • Publication number: 20040022091
    Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 5, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
  • Publication number: 20030224113
    Abstract: A solution film-forming method including the steps of forming a film from a polymer solution in which a polymer is dissolved in an organic solvent transporting the film formed and passing the film through a drying area in which the film is heated to volatilize the organic solvent in the film to obtain a polymer film, wherein the film is passed through the drying area under the condition of −0.05≦&egr;MD-&egr;TD<+0.15, where a degree of stretching of the film in the transport direction within the drying area during transport is expressed as &egr;MD and a degree of stretching of the film in the width direction within the drying area during transport is expressed as &egr;TD.
    Type: Application
    Filed: June 4, 2003
    Publication date: December 4, 2003
    Inventors: Toshikazu Nakamura, Hidekazu Yamazaki
  • Publication number: 20030219649
    Abstract: A nonaqueous electrolyte secondary battery including a battery case that is not corroded easily even at the time of over-discharging is provided. The nonaqueous electrolyte secondary battery includes a battery case serving as a negative electrode terminal, and a positive electrode, a negative electrode, a separator and a nonaqueous electrolyte that are enclosed in the battery case. The positive electrode and the negative electrode respectively include an active material that stores and releases lithium reversibly. The battery case includes a case formed of a metal plate having iron as a principal component and a metal layer formed at least in a part of an inner surface of the case, and the metal layer includes a metallic element M that dissolves in the nonaqueous electrolyte at a lower potential than iron and at a higher potential than lithium.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 27, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masashi Shoji, Emiko Igaki, Masakazu Tanahashi, Toshikazu Nakamura, Mikinari Shimada
  • Patent number: 6628564
    Abstract: A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: September 30, 2003
    Assignee: Fujitsu Limited
    Inventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
  • Publication number: 20030173703
    Abstract: A production method of cellulose film wherein cellulose film is produced by preparing a polymer solution through dissolving cellulose ester in a solvent containing a prescribed organic solvent as the main component, forming a filmy object from the prepared polymer solution, and evaporating the solvent in the filmy object; the residual amount of the organic solvent is reduced while the film quality is not degraded, and the production efficiency is degraded to a least possible extent; a poor solvent, highest in boiling point among the materials contained in the solvent, is added in the content ranging from 0.1 wt % to 1.0 wt %, taking the total amount of the solvent in the prepared polymer solution to be 100 wt %; and the solubility of cellulose ester in the poor solvent is inferior to the solubility of the cellulose ester in the organic solvent which is the main component of the solvent.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 18, 2003
    Applicant: FUJI PHOTO FILM CO., LTD
    Inventors: Hidekazu yamazaki, Toshikazu Nakamura, Hiroshi Miyachi
  • Publication number: 20030176347
    Abstract: The invention presents a therapeutic agent (and progress suppressant) for amyotrophic lateral sclerosis (ALS) containing HGF and/or HGF gene as active ingredient. HGF has an effect of improving the motor function of ALS and life span through two actions, that is, direct neuronutrient factor activity on motoneurons, and indirect improving action of glutamate cytotoxicity on motoneurons by maintaining the level of glutamate transporter in astrocytes. Hence, HGF and/or HGF gene can be used as an effective therapeutic agent not known in the past.
    Type: Application
    Filed: May 14, 2003
    Publication date: September 18, 2003
    Inventors: Toshikazu Nakamura, Hiroshi Funakoshi, Woong Sun
  • Publication number: 20030162736
    Abstract: (Problems) The present invention provides a therapeutic agent which is effective for primary tumor of cancer and, more particularly, it provides an NK4 gene therapeutic agent and a recombinant NK4 protein preparation which is effective for the prevention and therapy of cancer. The present invention also provides a therapeutic agent which is effective for metastasis of cancer and, more particularly, it provides an NK4 gene therapeutic agent and a recombinant NK4 protein preparation which is effective for the prevention and therapy of metastasis of cancer.
    Type: Application
    Filed: September 27, 2002
    Publication date: August 28, 2003
    Inventors: Toshikazu Nakamura, Kunio Matsumoto
  • Patent number: 6605963
    Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: August 12, 2003
    Assignee: Fujitsu Limited
    Inventors: Ayako Kitamoto, Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Hideki Kanou, Kuninori Kawabata, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Publication number: 20030146950
    Abstract: A semiconductor memory device includes a first bit line connected to a memory cell via a transistor, a transfer gate, a second bit line connected to the first bit line via the transfer gate, a sense amplifier connected to the second bit line, a first precharge circuit for precharging the first bit line, a second precharge circuit for precharging the second bit line, a control circuit which precharges the first bit line by the first precharge circuit after closing the transfer gate, followed by subsequent precharging of the second bit line by the second precharge circuit.
    Type: Application
    Filed: October 10, 2002
    Publication date: August 7, 2003
    Applicant: Fujitsu Limited
    Inventors: Toshiya Miyo, Toshikazu Nakamura, Satoshi Eto, Ayako Sato, Masato Matsumiya
  • Publication number: 20030098522
    Abstract: A process and apparatus for solvent casting which comprises, casting a polymer solution onto a casting support, cooling the polymer solution to gelatinize on the casting support to form web, stripping off the web from the casting support, thrusting side edges of the web into pins of a pin tenter by an inserting device, and drying the web while conveying the web with carrying the side edges of the web by the pin tenter, wherein the inserting device is cooled so that the surface temperature of the web in contact with the inserting device does not exceed a gelation temperature of the polymer solution are proposed. The present invention makes surely to convey the web without slipping from the pin tenters even when the pin tenters convey the web at a high speed. As a result, the productivity of film can be improved.
    Type: Application
    Filed: October 1, 2002
    Publication date: May 29, 2003
    Inventors: Toshikazu Nakamura, Hidekazu Yamazaki
  • Patent number: 6548903
    Abstract: In the first and second regions data not concurrently transferred is transferred by using data lines having the respective different wiring layers. The vertical positions of the data lines are reversed between the first and second regions. In the switching regions the data lines are exchanged between the first and second regions. The parasitic capacitances associated with the two data lines are practically equal to each other so that the delay times of signals transferred along the data lines are equal to each other. This can prevent a circuit malfunction due to a parasitic capacitance difference. In the semiconductor integrated circuit where memory cell arrays and sense amplifier arrays are alternately wired, forming the first and second regions over the memory cell arrays and the switching regions over the sense amplifier arrays makes it easier to exchange the vertical positions of the data lines in the switching regions.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: April 15, 2003
    Assignee: Fujitsu Limited
    Inventors: Toshikazu Nakamura, Toshiya Miyo
  • Publication number: 20030065997
    Abstract: A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern(s) outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern(s) (the first test mode) generated within the logic chip or the external test pattern (the second test mode) supplied from the exterior.
    Type: Application
    Filed: April 16, 2002
    Publication date: April 3, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Masafumi Yamazaki, Takaaki Suzuki, Toshikazu Nakamura, Satoshi Eto, Toshiya Miyo, Ayako Sato, Takayuki Yoneda, Noriko Kawamura
  • Publication number: 20030060403
    Abstract: The invention relates to a therapeutic agent for disorder in brain and nerve containing HGF (hepatocyte growth factor) as an active ingredient, and a method for treatment of disorder in brain and nerve comprising administration of HGF. The active ingredient HGF possesses an action to prolong survival of brain and nerve cells, and the injured brain or nerves may be regenerated and restored. Therefore, the therapeutic agent and method for treatment of the invention are useful for prevention and treatment of various disorder in brain and nerve (for example, dementia, senile dementia of Alzheimer type, cerebral stroke, and cerebral infarction).
    Type: Application
    Filed: March 15, 1996
    Publication date: March 27, 2003
    Inventor: TOSHIKAZU NAKAMURA
  • Publication number: 20030025122
    Abstract: In the first and second regions data not concurrently transferred is transferred by using data lines having the respective different wiring layers. The vertical positions of the data lines are reversed between the first and second regions. In the switching regions the data lines are exchanged between the first and second regions. The parasitic capacitances associated with the two data lines are practically equal to each other so that the delay times of signals transferred along the data lines are equal to each other. This can prevent a circuit malfunction due to a parasitic capacitance difference. In the semiconductor integrated circuit where memory cell arrays and sense amplifier arrays are alternately wired, forming the first and second regions over the memory cell arrays and the switching regions over the sense amplifier arrays makes it easier to exchange the vertical positions of the data lines in the switching regions.
    Type: Application
    Filed: February 6, 2002
    Publication date: February 6, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Toshikazu Nakamura, Toshiya Miyo
  • Patent number: 6514631
    Abstract: A heating furnace tube, a method of using the same and a method of manufacturing the same which have been developed with a view to eliminating inconveniences occurring when a carbon-containing fluid is made to flow in the heating furnace tube. The heating furnace tube which comprises a rare earth oxide particle distributed iron alloy containing 17-26 wt. % of Cr and 2-6 wt. % of Al. The method of manufacturing this heating furnace tube which comprises the steps of forming or inserting an insert metal on or into at least one of a joint end portion of one heating furnace tube element and that of the other heating furnace tube element, bringing these two joint end portions into pressure contact with each other directly or via an intermediate member, and diffusion welding the two heating furnace tube elements to each other by heating the insert metal.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: February 4, 2003
    Assignee: JGC Corporation
    Inventors: Katsumi Yamamoto, Takeo Murata, Rin Sasano, Kenji Sato, Toshikazu Nakamura, Muneyasu Ichimura, Kunio Ishii, Keizo Hosoya