Patents by Inventor Toshikazu Nakamura

Toshikazu Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6201378
    Abstract: A semiconductor integrated circuit producing a given output voltage includes first and second operational amplifiers, and first and second transistors. The first and second operational amplifiers detect a voltage difference between a voltage applied to an input terminal and at least one reference voltage. The first and second transistors are turned ON or turned OFF according to the levels of voltages output from the first and second operational amplifiers. The first operational amplifier receives the output voltage at the input terminal. When the level of the output voltage becomes lower than the reference voltage, the first operational amplifier allows the first transistor to operate so as to raise the output voltage. In contrast, the second operational amplifier receives the output voltage at the input terminal. When the level of the output voltage exceeds the reference voltage, the second operational amplifier allows the second transistor to operate so as to lower the output voltage.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: March 13, 2001
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masato Matsumiya, Masato Takita, Toshikazu Nakamura, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Patent number: 6172537
    Abstract: A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: January 9, 2001
    Assignee: Fujitsu Limited
    Inventors: Hideki Kanou, Masato Matsumiya, Satoshi Eto, Masato Takita, Ayako Kitamoto, Toshikazu Nakamura, Kuninori Kawabata, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Patent number: 6150866
    Abstract: A clock supplying circuit that supplies a clock to a plurality of controlled circuits 451-454 arranged in respectively different positions. A forward and backward wiring 41, 42 and an internal clock supply wiring 43 are arranged along controlled circuits. A main clock drive circuit 40 is for outputting a first clock to the forward wiring 41 and is for outputting a second shorter phase than the first clock to the internal clock supply wiring 43. A plurality of local clock drive circuits 441-444 arranged close to the controlled circuits, are supplied with a forward clock propagated along the forward wiring and with a back clock propagated along the backward wiring, and are also supplied with the second clock, for delaying the phase of the supplied second clock so as to coincide with a phase intermediate the forward clock and the back clock, and for supplying the delayed clock of the second clock to the respectively corresponding controlled circuits as local clock.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: November 21, 2000
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Toshikazu Nakamura
  • Patent number: 6147919
    Abstract: A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Kuninori Kawabata, Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Masatomo Hasegawa, Hideki Kanou, Ayako Kitamoto, Toru Koga, Yuki Ishii, Akira Kikutake, Yuichi Uzawa
  • Patent number: 6134771
    Abstract: An electronic part in which insulating tape is adhered to lead terminals which extend from an electronic part unit so that a pitch between the terminals can remain stable and constant. The insulating tape is adhered to portions of the lead terminals in a vicinity of the unit from both sides such that the tape is placed with the terminals therebetween.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: October 24, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshikazu Nakamura, Takashi Shikama
  • Patent number: 6115284
    Abstract: The present invention relates to a memory device including memory cells each formed of a cell transistor connected to bit and word line and a cell capacitor. The memory device includes a pre-charging circuit for pre-charging bit line to a first voltage, a sense amplifier for detecting voltages of bit lines and driving the bit lines to a second voltage for H level or a third voltage for L level, and a word line driving circuit for driving word lines to make the writing voltage for H level of the cell capacitor to a fourth voltage lower than the second voltage. The present invention is characterized in that the first voltage is lower than an intermediate value between the second and third voltages. According to the present invention, it becomes possible to prevent the voltage V.sub.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: September 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Patent number: 6111802
    Abstract: A semiconductor memory device includes a memory cell connected to a bit line and a word line, a bit line precharge circuit which precharges the bit line to a ground voltage, and a word decoder which sets the word line to a negative voltage when the word line is not selected.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: August 29, 2000
    Assignee: Fujitsu Limited
    Inventors: Hideki Kano, Masato Matsumiya, Masato Takita, Toru Koga, Satoshi Eto, Toshikazu Nakamura, Mitsuhiro Higashiho, Kuninori Kawabata, Ayako Kitamoto
  • Patent number: 6070911
    Abstract: A clamp-type isolating pipe joint is disclosed, which can connect pipes by providing insulation between them, is easy to assemble and disassemble, has high reliability and allows easy replacement of parts and is inexpensive to manufacture and install. The joint comprises hubs weldable to connectable pipes, a seal ring interposed between butted surfaces of the hubs and a clamp disposed around the circumferences of the hubs for clamping itself with bolts in the radial direction of the hubs to be fixed as insulated from each other. The clamp and hubs are insulated by interposing between them a metal plate with an insulating resin coat formed thereon. Insulation layers are also provided between the seal ring and the hubs.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: June 6, 2000
    Assignee: JGC Corporation
    Inventors: Yasuo Namikawa, Toshikazu Nakamura, Keizo Hosoya, Muneyasu Ichimura
  • Patent number: 6072749
    Abstract: This invention is a memory device with a structure that has eliminated the logic circuit using I/O mask signal DQM from within the critical path from the clock CLK to the predecoder and column decoder for generating column selection signal CL. The logic circuit using I/O mask signal DQM within the critical path for generating column selection signals is eliminated, and the time from when the clock is supplied until the column selection signal is generated is made as short as possible. On the other hand, to make an I/O mask possible during burst write mode, drive control of the write amplifier is performed based on I/O mask signal DQM. Specifically, activation of the write amplifier is prohibited or allowed in response to the I/O mask signal DQM.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: June 6, 2000
    Assignee: Fujitsu Limited
    Inventors: Toshikazu Nakamura, Masato Matsumiya, Satoshi Eto, Masato Takita, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Patent number: 6049239
    Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: April 11, 2000
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima
  • Patent number: 6036972
    Abstract: The invention describes to a method of treating a patient with dilated cardiomyopathy comprising administering an effective amount of Hepatocyte Growth Factor (HGF).
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: March 14, 2000
    Inventors: Toshikazu Nakamura, Kazuo Komamura, Kunio Miyatake
  • Patent number: 5997717
    Abstract: Disclosed herein is electrolyzed functional water produced by the process comprising a step of feeding water containing electrolytes to a first electrolytic cell equipped with an anode, a cathode and an ion-permeable membrane between them to electrolyze it, and a step of electrolyzing the electrolyzed water obtained from the cathodic side of the first electrolytic cell on the anodic side of a second electrolytic cell equipped with an anode, a cathode and an ion-permeable membrane between them. Production processes and production apparatus of the electrolyzed functional water are also disclosed.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: December 7, 1999
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Kohichi Miyashita, Keiji Nagano, Toshikazu Nakamura
  • Patent number: 5943253
    Abstract: A semiconductor memory device includes at least one cell block including an array of memory cells, a plurality of sense amplifiers which temporarily hold data of the memory cells, a first data bus connected to the plurality of sense amplifiers via first gates, and a second data bus having a direct electrical connection to the first data bus and being laid out to extend through a position of the at least one cell block.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: August 24, 1999
    Assignee: Fujitsu Limited
    Inventors: Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata
  • Patent number: 5936912
    Abstract: An electronic device includes a first circuit which refers to an external clock and thus produces a first internal clock, and a second circuit which refers to the first internal clock and thus produces a second internal clock. The first circuit has a first phase error between the external clock and the first internal clock, and the second circuit has a second phase error between the first internal clock and the second internal clock. The first phase error has a sign reverse to that of the second phase error.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: August 10, 1999
    Assignee: Fujitsu Limited
    Inventors: Kuninori Kawabata, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Mitsuhiro Higashiho, Masato Takita, Toru Koga, Hideki Kanou, Ayako Kitamoto
  • Patent number: 5924656
    Abstract: A thermal insulating supporting device for piping has a supporting member which is formed by cutting to specified dimensions a long member which has a specified cross-sectional shape, and which is made of a resin material that has heat-insulating properties and sufficient strength to support piping. The supporting device supports piping by connecting the supporting member to a supporting frame which is fastened to the piping.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: July 20, 1999
    Assignee: JGC Corporation
    Inventors: Akira Okada, Mamoru Morohashi, Toshikazu Nakamura, Satoshi Hama
  • Patent number: 5916628
    Abstract: A cell that is excellent in discharge characteristics and cycle characteristics is provided by filtering an active material paste, which contains an active material, a binder resin solution, and a conducting agent added as required, at least one time by a filter while stirring the active material paste in a stirring apparatus that has a stirring blade, and then coating a current collector with the active material paste. An active material paste is circulated and filtered by a feeding pump and a filter while being stirred in a stirring apparatus that has a stirring blade. Then, the active material paste is fed to another filter by a metering pump and filtered, and then, a current collector (backing) is coated with the active material paste. Then, the active material paste is dried in a dry zone and taken up by a take-up roller.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: June 29, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Ueyama, Kunio Tsuruta, Yorihito Ohana, Toshikazu Nakamura
  • Patent number: 5840311
    Abstract: The present invention relates to an agent accelerating collagen decomposition and a therapeutic agent for fibrosis disorder containing HGFs (Hepatocyte Growth Factors) as an active ingredient. The active ingredients HGFs accelerate the decomposition of collagen (increase of collagenase activity), and can effectively treat fibrosis disorder by the acceleration of collagen decomposition. Therefore, according to the present invention, the prevention and treatment of a disease due to reduced collagenase activity and fibrosis disorders characterized by excessive production of fibroblast-derived connective tissue matrix are possible.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: November 24, 1998
    Assignees: Toshikazu Nakamura, Snow Brand Milk Products Co., Ltd., Sumitomo Pharmaceuticals Co., Ltd.
    Inventors: Toshikazu Nakamura, Akira Shiota, Nobuaki Fujise, Mitsuo Namiki
  • Patent number: 5824156
    Abstract: Roll 13 drives base material 12 run continuously, and nozzle 1 applies paint 11 supplied by head 2 on base material intermittently. Head 2 shuts the flow of paint 11 to nozzle 1, when application of paint 11 is suspended, and guides to a place other than nozzle 1, at the same time sucks paint 11 staying in the inside of nozzle 1 and at the exit of slit 7 to sucking part 25 provided in inside of nozzle 1; when application of paint 11 is resumed, releases the flow of paint 11 to nozzle 1, at the same time returns paint 11 that was sucked in sucking part 25 to the inside of nozzle 1; thereby the starting edge and the ending edge of coated areas intermittently applied on the base material can be made to assume a straight line shape, and occurrence of the thicker coating at the starting edge is also prevented.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: October 20, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaru Watanabe, Yasuhiro Ueyama, Toshikazu Nakamura, Yorihito Ohana, Tetsuya Hayashi
  • Patent number: 5776464
    Abstract: The present invention relates to an agent for relieving side effects caused by immunosuppressants, which comprises HGF (Hepatocyte growth factor) as an active component, a method for relieving side effects caused by immunosuppressants, which comprises administration of HGF and use of HGF for producing an agent for relieving the side effects. HGF as an active component can reduce multiple-organ or systemic side effects caused by immunosuppressants. Therefore, according to the present invention, restrictions of use and dose of immunosuppressants are reduced, success rate of organ transplantation and cure rate of various patients to which the immunosuppressants are administered can be improved and at the same time burden of the patients can be remarkably reduced.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: July 7, 1998
    Inventor: Toshikazu Nakamura
  • Patent number: 5426584
    Abstract: In a steering control system for a moving body in which azimuths of reference points are detected by rotatively scanning a light beam around the moving body, a current position of the moving body is calculated based on the azimuths of reference points, and the moving body is steered so that the current position thereof follows a predetermined travelling course that is calculated in accordance with an algorithm previously stored in a memory. The system assigns each detected reference point to each reference point in said algorithm for calculating the relative traveling course, based on one of a reference point that is detected first under the condition that the azimuth exceeds a first predetermined angle, and a reference point that is detected last with the azimuth being less than a second predetermined angle when the azimuth is measured with respect to the advance direction of the moving vehicle initially placed in the traveling area before the start of a work.
    Type: Grant
    Filed: February 9, 1993
    Date of Patent: June 20, 1995
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Kenji Kamimura, Sadachika Tsuzuki, Toshikazu Nakamura