Patents by Inventor Toshiya Uchida
Toshiya Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7741723Abstract: In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second interconnection terminal thereof connected to a first interconnection terminal of the first chip. First and second external terminals of the first and second chips are formed on surfaces of the first and second chips, the surface being on a same side of the first and second chips. Therefore, even after the first chip and the second chip are pasted together, it is possible to test the first chip and the second chip while operating them independently. Further, since test probes or the like can be brought into contact with the external terminals of the first chip and the second chip from the same side, it is possible to simultaneously test the first chip and the second chip.Type: GrantFiled: February 20, 2007Date of Patent: June 22, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Toshiya Uchida
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Publication number: 20100146201Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: November 4, 2009Publication date: June 10, 2010Applicant: FUJITSU LIMITEDInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7729200Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: GrantFiled: December 18, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20100128539Abstract: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.Type: ApplicationFiled: November 24, 2009Publication date: May 27, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroyuki KOBAYASHI, Toshiya UCHIDA
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Patent number: 7668040Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: GrantFiled: February 16, 2007Date of Patent: February 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7508252Abstract: A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.Type: GrantFiled: August 16, 2006Date of Patent: March 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Masafumi Yamazaki, Toshiya Uchida
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Publication number: 20090027988Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: December 19, 2007Publication date: January 29, 2009Applicant: Toyoda Gosei Co., Ltd.Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7483331Abstract: A memory system includes a semiconductor memory having a plurality of banks; and a controller accessing the semiconductor memory. The number of the banks is larger than the number of banks simultaneously accessed. When receiving an access command for the bank currently executing the access operation, the semiconductor memory activates a busy signal and keeps the busy signal active until the access operation currently executed is completed. The controller stops outputting a next access command while receiving the activated busy signal. Based on the received busy signal, the controller judges whether or not the next access command should be outputted to the semiconductor memory. Consequently, it is possible to easily execute the random access in a semiconductor memory having a plurality of banks, without giving any load to the system side, which can improve the data transfer rate at the time of the random access.Type: GrantFiled: June 20, 2006Date of Patent: January 27, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Toshiya Uchida
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Publication number: 20080189467Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: ApplicationFiled: December 18, 2007Publication date: August 7, 2008Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080181027Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: December 19, 2007Publication date: July 31, 2008Inventors: Takahiro Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151677Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: January 26, 2007Publication date: June 26, 2008Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151670Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: February 23, 2007Publication date: June 26, 2008Inventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151678Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: ApplicationFiled: February 16, 2007Publication date: June 26, 2008Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7369443Abstract: A semiconductor device includes a terminal configured to receive a first signal that is set from an exterior at a time of operation, a memory unit configured to retain a state of a setting fixedly regardless of whether at the time of operation or at a time of no operation and to produce at an output thereof a second signal responsive to the state of a setting, and an output driver unit coupled to the terminal and to the output of the memory unit to output an output signal by a drive power responsive to the first signal and the second signal.Type: GrantFiled: June 14, 2005Date of Patent: May 6, 2008Assignee: Fujitsu LimitedInventors: Hiroyuki Kobayashi, Toshiya Uchida
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Publication number: 20080104458Abstract: A plurality of test patterns generated by a test pattern generator is output from a first memory chip to test a second memory chip, which is of a different type from the first memory chip and mounted in the same package. Therefore, when different types of memory chips are mounted in the same package, the memory chip is tested even no terminal of the memory chip is connected to an external terminal of a system. Since there is no need to form any useless terminal in the system, system cost is reduced. Since a testing apparatus generating complicated test patterns is made unnecessary, test cost is reduced. The test pattern generator is constructed using nonvolatile logic and therefore, tests can be carried out without preparing test patterns in advance. Consequently, a user who purchases the first and second memory chips to construct a system can also carry out tests easily.Type: ApplicationFiled: October 19, 2007Publication date: May 1, 2008Inventor: Toshiya Uchida
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Patent number: 7323789Abstract: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.Type: GrantFiled: January 28, 2005Date of Patent: January 29, 2008Assignee: Fujitsu LimitedInventors: Fusao Seki, Tatsushi Otsuka, Masanori Kurita, Shinnosuke Kamata, Toshiya Uchida, Hiroyoshi Tomita, Hiroyuki Kobayashi
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Publication number: 20080001305Abstract: In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second interconnection terminal thereof connected to a first interconnection terminal of the first chip. First and second external terminals of the first and second chips are formed on surfaces of the first and second chips, the surface being on a same side of the first and second chips. Therefore, even after the first chip and the second chip are pasted together, it is possible to test the first chip and the second chip while operating them independently. Further, since test probes or the like can be brought into contact with the external terminals of the first chip and the second chip from the same side, it is possible to simultaneously test the first chip and the second chip.Type: ApplicationFiled: February 20, 2007Publication date: January 3, 2008Inventor: Toshiya Uchida
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Publication number: 20070217278Abstract: A memory system includes a semiconductor memory having a plurality of banks; and a controller accessing the semiconductor memory. The number of the banks is larger than the number of banks simultaneously accessed. When receiving an access command for the bank currently executing the access operation, the semiconductor memory activates a busy signal and keeps the busy signal active until the access operation currently executed is completed. The controller stops outputting a next access command while receiving the activated busy signal. Based on the received busy signal, the controller judges whether or not the next access command should be outputted to the semiconductor memory. Consequently, it is possible to easily execute the random access in a semiconductor memory having a plurality of banks, without giving any load to the system side, which can improve the data transfer rate at the time of the random access.Type: ApplicationFiled: June 20, 2006Publication date: September 20, 2007Inventor: Toshiya Uchida
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Patent number: 7221574Abstract: A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected to said bit lines, amplifying data on the bit lines; and a switching transistor (505a) connecting or disconnecting the bit line connected to the memory cell to or from the bit line connected to the sense amplifier. The switching transistor operates differently in a first memory cell access operation and in a second memory cell access operation.Type: GrantFiled: April 12, 2005Date of Patent: May 22, 2007Assignee: Fujitsu LimitedInventors: Hiroyoshi Tomita, Toshiya Uchida
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Publication number: 20070058451Abstract: The invention relates to a semiconductor memory device and a semiconductor integrated circuit system using the same and a control method of a semiconductor memory device. An object of the invention is to provide a semiconductor memory device which reduces the number of accesses to decrease the burden on a control unit and facilitates circuit board design, a semiconductor integrated circuit system using the same, and a control method of a semiconductor memory device. The semiconductor memory device is configured to have a data input unit to which input data is inputted from outside, a memory unit which stores data, an operation unit which processes a predetermined operation on input data and read data read out from the memory unit, and a data output unit which outputs operation result data obtained at the operation unit to the outside.Type: ApplicationFiled: February 9, 2006Publication date: March 15, 2007Inventor: Toshiya Uchida