Abstract: A switch circuit having a high withstanding voltage and low driving ability and another switch circuit having a low withstanding voltage and high driving ability are connected to a specified node in parallel. When discharging the charges of the specified node, the switch circuit having the high withstanding voltage is turned ON and the switch circuit having the great driving ability is then turned ON. Accordingly, it is sufficient that only the transition of the logical voltage of a switch circuit having the high withstanding voltage is taken into consideration to set the ON timing of a switch circuit having the high driving ability. Consequently, timing setting can be performed easily. After the switch circuit having the high driving ability is turned ON, a discharge path for the charges of the specified node takes two paths which passes through both switch circuits in parallel. Consequently, an operating speed can be increased.

Abstract: A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.

Abstract: A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be a higher response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

Abstract: A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

Abstract: A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

Abstract: Two semiconductor chips are coupled to outer leads by means of tape leads so that the chips are spaced apart from each other. A space between the chips is filled with a mold resin.

Abstract: A semiconductor device includes lead frames (21) respectively having first main surfaces and second main surfaces opposite to each other, bonding being able to be performed on the first and second main surfaces, a first semiconductor chip (22) arranged on first main surface sides of the lead frames, first tape leads (23) electrically connecting the first main surfaces of the lead frames to the first semiconductor chip, a second semiconductor chip (24) arranged on second main surface sides of the lead frames, and second tape leads (25) electrically connecting the second main surfaces of the lead frames to the second semiconductor.

Abstract: A process wherein the parts of a lead frame that are outside a cavity are directly supported by ejecting pins extending from above and from below when the lead frame is sandwiched between an upper die and a lower die. The ejecting pins eject the lead frame, on which a package is formed, after a resin mold process.