Patents by Inventor Toshiyuki Honda
Toshiyuki Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040030823Abstract: To provide a nonvolatile storage device and control method thereof which improve convenience of portable devices by shortening initialization time.Type: ApplicationFiled: April 24, 2003Publication date: February 12, 2004Inventors: Toshiyuki Honda, Tetsushi Kasahara, Masayuki Toyama, Teruo Akashi, Keisuke Sakai
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Publication number: 20030222344Abstract: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.Type: ApplicationFiled: January 28, 2003Publication date: December 4, 2003Applicant: FUJITSU LIMITEDInventors: Sumikazu Hosoyamada, Yoshitsugu Kato, Mitsuo Abe, Kazuto Tsuji, Masaharu Minamizawa, Toshio Hamano, Toshiyuki Honda, Katsuro Hiraiwa, Masashi Takenaka
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Publication number: 20030160626Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.Type: ApplicationFiled: March 21, 2003Publication date: August 28, 2003Applicant: FUJITSU LIMITEDInventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
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Patent number: 6563330Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.Type: GrantFiled: March 31, 2000Date of Patent: May 13, 2003Assignee: Fujitsu LimitedInventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
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Publication number: 20030071342Abstract: A semiconductor device includes a resin housing provided with a functional part, a wire pattern made of a conductive material and molded in the resin housing, a part of the wire pattern being exposed from the resin housing, an electronic part connected with the wire pattern in a state where the electronic parts is molded in the resin housing, and a semiconductor element connected to the part of the wire pattern being exposed from the resin housing. The semiconductor element provides a designated function in cooperation with a functional part of the resin housing.Type: ApplicationFiled: March 28, 2002Publication date: April 17, 2003Applicant: FUJITSU LIMITEDInventors: Toshiyuki Honda, Kazuto Tsuji, Masanori Onodera, Hiroshi Aoki, Izumi Kobayashi, Susumu Moriya, Hiroshi Kaiya
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Patent number: 6509592Abstract: A ferroelectric memory includes a well region, which is defined in a semiconductor substrate and extends in a direction, a bit line also extending in the direction and a source line also extending in the direction. First, second and third memory cells are formed in this order on the well region and arranged in the direction. A first active region electrically connects the first memory cell and the bit line together. A second active region electrically connects the first memory cell and the source line together. A third active region electrically connects the second memory cell and the bit line together. A fourth active region electrically connects the second memory cell and the source line together. A fifth active region electrically connects the third memory cell and the bit line together. And a sixth active region electrically connects the third memory cell and the source line together.Type: GrantFiled: December 8, 2000Date of Patent: January 21, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshiyuki Honda
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Patent number: 6476417Abstract: A semiconductor device for picking up an image includes a lens-mounting unit provided with a lens for picking up an image; a semiconductor chip having a light-receiving element formed on a circuit-forming surface thereof, the light-receiving element converting light from the lens into an image signal; a flexible substrate provided between the lens-mounting unit and the semiconductor chip so as to supply the image signal to an external circuit; and a shading plate blocking light transmitting through the flexible substrate toward the semiconductor chip so as to substantially remove an influence of the light on the light-receiving element.Type: GrantFiled: March 28, 2001Date of Patent: November 5, 2002Assignee: Fujitsu LimitedInventors: Toshiyuki Honda, Susumu Kida, Hideo Suzuki
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Patent number: 6460773Abstract: A module of a combination card can be incorporated into a card body with solder being easily melted, and heat transmission to portions other than the antenna connection terminals is reduced. A card body is provided with an antenna. The module includes a substrate which has a terminal surface on which at least one external connection terminal is formed and a mounting surface opposite to the terminal surface. An IC chip is mounted on the mounting surface. The module includes at least one antenna connection terminal located on the mounting surface. The antenna connection terminal is connected to the antenna, and at least a part of the antenna connection terminal is exposed on the terminal surface.Type: GrantFiled: September 13, 2000Date of Patent: October 8, 2002Assignee: Fujitsu LimitedInventors: Hiroshi Kaiya, Toshiyuki Honda
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Publication number: 20020135068Abstract: A ferroelectric memory includes a well region, which is defined in a semiconductor substrate and extends in a direction, a bit line also extending in the direction and a source line also extending in the direction. First, second and third memory cells are formed in this order on the well region and arranged in the direction. A first active region electrically connects the first memory cell and the bit line together. A second active region electrically connects the first memory cell and the source line together. A third active region electrically connects the second memory cell and the bit line together. A fourth active region electrically connects the second memory cell and the source line together. A fifth active region electrically connects the third memory cell and the bit line together. And a sixth active region electrically connects the third memory cell and the source line together.Type: ApplicationFiled: December 8, 2000Publication date: September 26, 2002Inventor: Toshiyuki Honda
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Publication number: 20020119658Abstract: A semiconductor device includes a resin housing provided with a functional part, a wire pattern made of a conductive material and molded in the resin housing, a part of the wire pattern being exposed from the resin housing, an electronic part connected with the wire pattern in a state where the electronic parts is molded in the resin housing, and a semiconductor element connected to the part of the wire pattern being exposed from the resin housing. The semiconductor element provides a designated function in cooperation with a functional part of the resin housing.Type: ApplicationFiled: December 12, 2001Publication date: August 29, 2002Applicant: Fujitsu LimitedInventors: Toshiyuki Honda, Kazuto Tsuji, Masanori Onodera, Hiroshi Aoki, Izumi Kobayashi, Susumu Moriya, Hiroshi Kaiya
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Publication number: 20020089870Abstract: A ferroelectric memory has a plurality of memory cells each having a transistor and a ferroelectric capacitor arranged in a matrix. Plate lines run in the word line direction above the ferroelectric capacitors of memory cells adjacent to each other in the word line direction among the plurality of memory cells. Bit line contacts each for connecting a bit line and an active region of the transistor are placed in regions between the plate lines adjacent to each other in the bit line direction and between the ferroelectric capacitors adjacent to each other in the word line direction. Cuts are formed at positions of the plate lines near the bit line contacts. The active regions of the transistors of the plurality of memory cells extend in directions intersecting with the word line direction and the bit line direction.Type: ApplicationFiled: November 20, 2001Publication date: July 11, 2002Inventor: Toshiyuki Honda
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Publication number: 20020047119Abstract: A semiconductor device for picking up an image comprises a lens-mounting unit provided with a lens for picking up an image; a semiconductor chip having a light-receiving element formed on a circuit-forming surface thereof, the light-receiving element converting light from the lens into an image signal; a flexible substrate provided between the lens-mounting unit and the semiconductor chip so as to supply the image signal to an external circuit; and a shading plate blocking light transmitting through the flexible substrate toward the semiconductor chip so as to substantially remove an influence of the light on the light-receiving element.Type: ApplicationFiled: March 28, 2001Publication date: April 25, 2002Applicant: FUJITSU LIMITEDInventors: Toshiyuki Honda, Susumu Kida, Hideo Suzuki
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Publication number: 20020008263Abstract: A memory cell transistor using a word line WL as the gate thereof is provided in an active region OD, and a ferroelectric capacitor, including bottom electrode, ferroelectric film and top electrode TE, is formed on a field oxide film. A first interconnection layer is made up of storage lines, each connecting the top electrode TE to one of doped layers of the memory cell transistor, and bit lines, each of which is connected to the other doped layer. In a planar layout, the storage line-intersects only one side of the top electrode TE and the bit line BL does not overlap with the top electrode TE. Thus, it is possible to prevent the retention characteristics of the ferroelectric capacitor from being deteriorated due to the stress applied by the first interconnection layer to the ferroelectric capacitor. As a result, the reliability of a ferroelectric memory device, including, in a memory cell, a ferroelectric capacitor with a ferroelectric film interposed between the bottom and top electrodes, can be improved.Type: ApplicationFiled: June 15, 1999Publication date: January 24, 2002Inventors: HIROSHIGE HIRANO, TOSHIYUKI HONDA
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Patent number: 6081036Abstract: A semiconductor device is provided wich includes a first wiring and second wirings in which end portions of the second wirings connected to the first wiring are bent parallel to that forms a predetermined angle with respect to the first direction. The first wiring extends along a first direction and has a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside. The second wirings are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring.Type: GrantFiled: March 9, 1998Date of Patent: June 27, 2000Assignee: Matsushita Electronics Corp.Inventors: Hiroshige Hirano, Toshiyuki Honda
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Patent number: 6069408Abstract: A method of manufacturing a semiconductor device includes the steps of: mounting a semiconductor chip on a holding board having electrode accommodation recesses formed thereon, and mounting electrode members to the electrode accommodation recesses, the electrode members being formed separately from the semiconductor element; electrically connecting electrode pads formed on the semiconductor chip with the electrode members; forming a resin package for sealing the semiconductor chip on the holding board by using a die, the holding board serving as a part of the die; and separating the resin package including the electrode members from the holding board.Type: GrantFiled: January 14, 1999Date of Patent: May 30, 2000Assignee: Fujitsu LimitedInventors: Toshiyuki Honda, Akihiro Oku, Takanori Watanabe, Kazuto Tsuji, Yoshiyuki Yoneda
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Patent number: 5920509Abstract: By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.Type: GrantFiled: July 3, 1997Date of Patent: July 6, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshige Hirano, Toshiyuki Honda
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Patent number: 5891758Abstract: A method of manufacturing a semiconductor device includes the steps of: mounting a semiconductor chip on a holding board having electrode accommodation recesses formed thereon, and mounting electrode members to the electrode accommodation recesses, the electrode members being formed separately from the semiconductor element; electrically connecting electrode pads formed on the semiconductor chip with the electrode members; forming a resin package for sealing the semiconductor chip on the holding board by using a die, the holding board serving as a part of the die; and separating the resin package including the electrode members from the holding board.Type: GrantFiled: October 31, 1997Date of Patent: April 6, 1999Assignee: Fujitsu Limited, Ltd.Inventors: Toshiyuki Honda, Akihiro Oku, Takanori Watanabe, Kazuto Tsuji, Yoshiyuki Yoneda
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Patent number: 5849600Abstract: The invention provides a method of diagnosing Alzheimer's disease in a human patient by measuring the amount of p33 present in a biological sample from a patient who may have Alzheimer's disease relative to the amount of p33 in a control sample from an unaffected human. Also included in the invention are diagnostic kits for Alzheimer's disease and methods of screening for effective therapeutics for Alzheimer's disease.Type: GrantFiled: November 10, 1993Date of Patent: December 15, 1998Assignee: The McLean Hospital CorporationInventors: Ralph Nixon, Toshiyuki Honda
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Patent number: 5841698Abstract: A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.Type: GrantFiled: August 26, 1996Date of Patent: November 24, 1998Assignee: Matsushita Electric Inudustrial Co., Ltd.Inventors: Hiroshige Hirano, Toshiyuki Honda
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Patent number: 5831904Abstract: By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.Type: GrantFiled: August 1, 1996Date of Patent: November 3, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshige Hirano, Toshiyuki Honda