Patents by Inventor Toshiyuki Kikuchi

Toshiyuki Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10503152
    Abstract: Described herein is a technique capable of improving the productivity of a substrate processing system including a plurality of process chambers. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including: (a) placing a storage container accommodating substrates on a loading port shelf; (b) transferring the substrates in a predetermined order from the storage container to process chambers capable of processing the substrates; (c) perform a substrate processing in the process chambers; (d) generating first count data corresponding to the processing chambers; (e) storing the first count data; (f) assigning transfer flag data to one of the process chambers next to another of the process chambers corresponding to a maximum count number of the first count data; and (g) transferring substrates accommodated in a next storage container of the storage container in the predetermined order based on the transfer flag data.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 10, 2019
    Assignee: Kokusai Electric Corporation
    Inventors: Naofumi Ohashi, Toshiyuki Kikuchi, Shun Matsui, Tadashi Takasaki
  • Publication number: 20190294151
    Abstract: Described herein is a technique capable of improving the productivity of a substrate processing system including a plurality of process chambers. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including: (a) placing a storage container accommodating substrates on a loading port shelf; (b) transferring the substrates in a predetermined order from the storage container to process chambers capable of processing the substrates; (c) perform a substrate processing in the process chambers; (d) generating first count data corresponding to the processing chambers; (e) storing the first count data; (f) assigning transfer flag data to one of the process chambers next to another of the process chambers corresponding to a maximum count number of the first count data; and (g) transferring substrates accommodated in a next storage container of the storage container in the predetermined order based on the transfer flag data.
    Type: Application
    Filed: September 19, 2018
    Publication date: September 26, 2019
    Inventors: Naofumi OHASHI, Toshiyuki KIKUCHI, Shun MATSUI, Tadashi TAKASAKI
  • Publication number: 20190221460
    Abstract: A technique is described that provides efficient production management of a substrate processing system that includes a substrate processing apparatus and a mobile terminal. The substrate processing apparatus includes: at least one reactor where a substrate is processed; a transfer chamber adjacent to at least one reactor; a detector that detects a state of at least one reactor, a state of the transfer chamber, and generates monitored apparatus information representing the state of at least one reactor, and the state of the transfer chamber.
    Type: Application
    Filed: September 27, 2018
    Publication date: July 18, 2019
    Applicant: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yasuhiro MIZUGUCHI, Toshiyuki KIKUCHI, Naofumi OHASHI, Tadashi TAKASAKI, Shun MATSUI
  • Patent number: 10340237
    Abstract: A method of manufacturing a high quality a semiconductor device, includes loading a substrate comprising a conductive film and an insulating film into a process chamber. The insulating film is formed around the conductive film to expose the conductive film. A process gas, which comprises a component that reacts with a desorbed gas generated from the insulating film is supplied into the process chamber which causes a protective film to be selectively formed on the insulating film.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 2, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Hideharu Itatani, Naofumi Ohashi, Toshiyuki Kikuchi
  • Publication number: 20190081014
    Abstract: A method of manufacturing a high quality a semiconductor device, includes loading a substrate comprising a conductive film and an insulating film into a process chamber. The insulating film is formed around the conductive film to expose the conductive film. A process gas, which comprises a component that reacts with a desorbed gas generated from the insulating film is supplied into the process chamber which causes a protective film to be selectively formed on the insulating film.
    Type: Application
    Filed: January 26, 2018
    Publication date: March 14, 2019
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hideharu ITATANI, Naofumi OHASHI, Toshiyuki KIKUCHI
  • Patent number: 10128128
    Abstract: A method of manufacturing a semiconductor device includes: (a) loading into a process chamber a substrate including: a wiring layer including a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wire insulating film electrically insulating the plurality of copper containing film and a recess formed between the plurality of copper-containing film; and a first diffusion barrier film formed on a first portion of a surface of the plurality of copper-containing films to suppress a diffusion of a component of the plurality of copper-containing film; and (b) supplying a silicon-containing gas into the process chamber to form a silicon-containing film on: a surface of the recess; and a second portion of the surface of the plurality of copper-containing films other than the first portion where the first diffusion barrier film is formed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 13, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi Takeda, Hiroshi Ashihara, Naofumi Ohashi, Toshiyuki Kikuchi
  • Publication number: 20180315651
    Abstract: Described herein is a technique capable of providing a semiconductor device having good characteristics. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including: (a) loading a substrate into a process chamber; and (b) forming a stacked etch stopper film by performing: (b-1) forming a first etch stopper film containing a first element and a second element by supplying a first element-containing gas and a second element-containing gas onto the substrate; and (b-2) forming a second etch stopper film containing the first element, the second element and a third element by supplying the first element-containing gas, the second element-containing gas and a third element-containing gas onto the first etch stopper film.
    Type: Application
    Filed: April 27, 2018
    Publication date: November 1, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi TAKEDA, Naofumi OHASHI, Toshiyuki KIKUCHI
  • Publication number: 20180298488
    Abstract: A film formation apparatus is configured so as to be equipped with: a film-forming chamber for forming a thin film using plasma on a substrate at a film formation position; an abnormal discharge-detecting section for detecting an abnormal discharge of the plasma; an imaging device for imaging abnormal plasma, which is the plasma when an abnormal discharge is detected, or an abnormal substrate surface, which is the substrate surface on which a thin film is formed when an abnormal discharge is detected; and a storage unit for storing the images taken by the imaging device.
    Type: Application
    Filed: September 22, 2014
    Publication date: October 18, 2018
    Inventors: Eiji SAKATA, Toshiyuki KIKUCHI, Satoru KASHIWAGI, Yasuo SERA
  • Patent number: 10090322
    Abstract: A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film, a channel hole formed in the laminated film, a charge trapping film formed on a surface in the channel hole, a first channel film formed on a surface of the charge trapping film, and a common source line exposed on the bottom of the channel hole; receiving information on a distribution of hole diameter of the channel hole; and forming a second channel film on a surface of the first channel film by supplying a first processing gas and a second processing gas to a center side and an outer peripheral side of the substrate, respectively, so as to correct the distribution of the hole diameter based on the information.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 2, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Toshiyuki Kikuchi, Atsushi Moriya, Masanori Nakayama, Takashi Nakagawa
  • Publication number: 20180197877
    Abstract: A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film, a channel hole formed in the laminated film, a charge trapping film formed on a surface in the channel hole, a first channel film formed on a surface of the charge trapping film, and a common source line exposed on the bottom of the channel hole; receiving information on a distribution of hole diameter of the channel hole; and forming a second channel film on a surface of the first channel film by supplying a first processing gas and a second processing gas to a center side and an outer peripheral side of the substrate, respectively, so as to correct the distribution of the hole diameter based on the information.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 12, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi SHIMAMOTO, Toshiyuki KIKUCHI, Atsushi MORIYA, Masanori NAKAYAMA, Takashi NAKAGAWA
  • Patent number: 9991179
    Abstract: Provided is a technique capable of obtaining a satisfactory yield for a semiconductor device with an air gap. The technique includes a method of manufacturing a semiconductor device, including: (a) receiving a thickness information of a wiring layer formed on a substrate including: a first interlayer insulation film; and the wiring layer disposed on the first interlayer insulation film, the wiring layer including: copper-containing films used as wiring; and an inter-wiring insulation film having trenches filled with the copper-containing films and insulating the copper-containing films; (b) placing the substrate on a substrate support installed in a process chamber; and (c) etching the wiring layer using an etching gas based on an etching control value corresponding to the thickness information of the wiring layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: June 5, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Naofumi Ohashi, Kazuyuki Toyoda, Satoshi Shimamoto, Toshiyuki Kikuchi
  • Publication number: 20170358506
    Abstract: Provided is a technique capable of obtaining a satisfactory yield for a semiconductor device with an air gap. The technique includes a method of manufacturing a semiconductor device, including: (a) receiving a thickness information of a wiring layer formed on a substrate including: a first interlayer insulation film; and the wiring layer disposed on the first interlayer insulation film, the wiring layer including: copper-containing films used as wiring; and an inter-wiring insulation film having trenches filled with the copper-containing films and insulating the copper-containing films; (b) placing the substrate on a substrate support installed in a process chamber; and (c) etching the wiring layer using an etching gas based on an etching control value corresponding to the thickness information of the wiring layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: December 14, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi OHASHI, Kazuyuki TOYODA, Satoshi SHIMAMOTO, Toshiyuki KIKUCHI
  • Publication number: 20170287731
    Abstract: A method of manufacturing a semiconductor device includes: (a) loading into a process chamber a substrate including: a wiring layer including a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wire insulating film electrically insulating the plurality of copper containing film and a recess formed between the plurality of copper-containing film; and a first diffusion barrier film formed on a first portion of a surface of the plurality of copper-containing films to suppress a diffusion of a component of the plurality of copper-containing film; and (b) supplying a silicon-containing gas into the process chamber to form a silicon-containing film on: a surface of the recess; and a second portion of the surface of the plurality of copper-containing films other than the first portion where the first diffusion barrier film is formed.
    Type: Application
    Filed: March 16, 2017
    Publication date: October 5, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi TAKEDA, Hiroshi ASHIHARA, Naofumi OHASHI, Toshiyuki KIKUCHI
  • Patent number: 9728431
    Abstract: The present invention provides a technique for improving the productivity of a processing apparatus including a plurality of process chambers. There is provided a technique including a method for manufacturing a semiconductor device including: (a) transferring a last remaining substrate stored in an xth storage unit of a plurality of storage units to an empty nth chamber in an mth processing unit of a plurality of processing units; and (b) transferring a first one of a plurality of substrates stored in an (x+1)th storage unit of the plurality of storage units to one of chambers in an (m+1)th processing unit of the plurality of processing units (where x, m and n are natural numbers).
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 8, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi Ohashi, Toshiyuki Kikuchi, Shun Matsui, Tadashi Takasaki
  • Patent number: 9698050
    Abstract: A method of manufacturing a semiconductor device includes loading, into a process chamber, a substrate including a first wiring layer having a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wiring insulating film insulating between the plurality of copper-containing films, and a void formed between the plurality of copper-containing films, and a first diffusion barrier film formed on a portion of an upper surface of the copper-containing films to suppress diffusion of a component of the copper-containing films, and forming a second diffusion barrier film configured to suppress diffusion of a component of the copper-containing films on a surface of another portion, on which the first diffusion barrier film is not formed, in the copper-containing films.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: July 4, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hiroshi Ashihara, Naofumi Ohashi, Tsuyoshi Takeda, Toshiyuki Kikuchi
  • Patent number: 9666494
    Abstract: The present disclosure provides a technique capable of suppressing a deviation in a characteristic of a semiconductor device. There is provided a technique includes: (a) receiving data representing a thickness distribution of a polished silicon-containing layer on a substrate comprising a convex structure whereon the polished silicon-containing layer is formed; (b) calculating, based on the data, a process data for reducing a difference between a thickness of a portion of the polished silicon-containing layer formed at a center portion of the substrate and that of the polished silicon-containing layer formed at a peripheral portion of the substrate; (c) loading the substrate into a process chamber; (d) supplying a process gas to the substrate; and (e) compensating for the difference based on the process data by activating the process gas with a magnetic field having a predetermined strength on the substrate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 30, 2017
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Atsuhiko Suda, Kazuyuki Toyoda, Toshiyuki Kikuchi
  • Publication number: 20170098561
    Abstract: A substrate processing apparatus includes a reception part configured to receive film thickness distribution data of a substrate on which a channel region, an insulating film on the channel region, and a first silicon-containing layer as a portion of a silicon-containing film on the insulating film are formed; a substrate mounting part configured to mount the substrate; and a gas supply part configured to supply a gas to form a second silicon-containing layer as a portion of the silicon-containing film on the first silicon-containing layer to have a film thickness distribution different from a film thickness distribution of the film thickness distribution data, thereby correcting a film thickness of the silicon-containing film.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi OHASHI, Satoshi TAKANO, Toshiyuki KIKUCHI
  • Publication number: 20170092517
    Abstract: The present invention provides a technique for improving the productivity of a processing apparatus including a plurality of process chambers. There is provided a technique including a method for manufacturing a semiconductor device including: (a) transferring a last remaining substrate stored in an xth storage unit of a plurality of storage units to an empty nth chamber in an mth processing unit of a plurality of processing units; and (b) transferring a first one of a plurality of substrates stored in an (x+1)th storage unit of the plurality of storage units to one of chambers in an (m+1)th processing unit of the plurality of processing units (where x, m and n are natural numbers).
    Type: Application
    Filed: December 28, 2015
    Publication date: March 30, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi OHASHI, Toshiyuki KIKUCHI, Shun MATSUI, Tadashi TAKASAKI
  • Publication number: 20170040232
    Abstract: A technique is provided in which a deviation of a characteristic of a semiconductor device is suppressed from occurring. The technique includes a method of a manufacturing a semiconductor device, including: (a) polishing a first silicon-containing layer formed on a substrate including a convex structure; (b) obtaining a data representing a height distribution of a surface of the first silicon-containing layer after performing the step (a); (c) determining a process condition; and (d) supplying a process gas to form a second silicon-containing layer wherein the process gas is activated such that a concentration of an active species of the process gas at a center portion of the substrate differs from a concentration of an active species at a peripheral portion of the substrate to adjust heights of surfaces of a laminated film according to the process condition.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 9, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Masanori NAKAYAMA, Toshiyuki KIKUCHI, Atsuhiko SUDA, Kazuyuki TOYODA, Shun MATSUI
  • Publication number: 20170040233
    Abstract: Deviation in properties of a semiconductor is suppressed. Provided is a configuration including a receiving member configured to receive data representing a film thickness distribution of a silicon-containing film formed on a substrate, a substrate support where the substrate is placed, a gas supply member configured to supply gases in a manner that a hard mask film having a film thickness distribution different from that of the silicon-containing film is formed on the silicon-containing film to maintain a height of an upper surface of the hard mask film in a predetermined range.
    Type: Application
    Filed: August 31, 2016
    Publication date: February 9, 2017
    Inventors: Naofumi OHASHI, Satoshi TAKANO, Toshiyuki KIKUCHI