Patents by Inventor Toshiyuki Kikuchi

Toshiyuki Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9728431
    Abstract: The present invention provides a technique for improving the productivity of a processing apparatus including a plurality of process chambers. There is provided a technique including a method for manufacturing a semiconductor device including: (a) transferring a last remaining substrate stored in an xth storage unit of a plurality of storage units to an empty nth chamber in an mth processing unit of a plurality of processing units; and (b) transferring a first one of a plurality of substrates stored in an (x+1)th storage unit of the plurality of storage units to one of chambers in an (m+1)th processing unit of the plurality of processing units (where x, m and n are natural numbers).
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 8, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi Ohashi, Toshiyuki Kikuchi, Shun Matsui, Tadashi Takasaki
  • Patent number: 9698050
    Abstract: A method of manufacturing a semiconductor device includes loading, into a process chamber, a substrate including a first wiring layer having a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wiring insulating film insulating between the plurality of copper-containing films, and a void formed between the plurality of copper-containing films, and a first diffusion barrier film formed on a portion of an upper surface of the copper-containing films to suppress diffusion of a component of the copper-containing films, and forming a second diffusion barrier film configured to suppress diffusion of a component of the copper-containing films on a surface of another portion, on which the first diffusion barrier film is not formed, in the copper-containing films.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: July 4, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hiroshi Ashihara, Naofumi Ohashi, Tsuyoshi Takeda, Toshiyuki Kikuchi
  • Patent number: 9666494
    Abstract: The present disclosure provides a technique capable of suppressing a deviation in a characteristic of a semiconductor device. There is provided a technique includes: (a) receiving data representing a thickness distribution of a polished silicon-containing layer on a substrate comprising a convex structure whereon the polished silicon-containing layer is formed; (b) calculating, based on the data, a process data for reducing a difference between a thickness of a portion of the polished silicon-containing layer formed at a center portion of the substrate and that of the polished silicon-containing layer formed at a peripheral portion of the substrate; (c) loading the substrate into a process chamber; (d) supplying a process gas to the substrate; and (e) compensating for the difference based on the process data by activating the process gas with a magnetic field having a predetermined strength on the substrate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 30, 2017
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Atsuhiko Suda, Kazuyuki Toyoda, Toshiyuki Kikuchi
  • Publication number: 20170098561
    Abstract: A substrate processing apparatus includes a reception part configured to receive film thickness distribution data of a substrate on which a channel region, an insulating film on the channel region, and a first silicon-containing layer as a portion of a silicon-containing film on the insulating film are formed; a substrate mounting part configured to mount the substrate; and a gas supply part configured to supply a gas to form a second silicon-containing layer as a portion of the silicon-containing film on the first silicon-containing layer to have a film thickness distribution different from a film thickness distribution of the film thickness distribution data, thereby correcting a film thickness of the silicon-containing film.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi OHASHI, Satoshi TAKANO, Toshiyuki KIKUCHI
  • Publication number: 20170092517
    Abstract: The present invention provides a technique for improving the productivity of a processing apparatus including a plurality of process chambers. There is provided a technique including a method for manufacturing a semiconductor device including: (a) transferring a last remaining substrate stored in an xth storage unit of a plurality of storage units to an empty nth chamber in an mth processing unit of a plurality of processing units; and (b) transferring a first one of a plurality of substrates stored in an (x+1)th storage unit of the plurality of storage units to one of chambers in an (m+1)th processing unit of the plurality of processing units (where x, m and n are natural numbers).
    Type: Application
    Filed: December 28, 2015
    Publication date: March 30, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi OHASHI, Toshiyuki KIKUCHI, Shun MATSUI, Tadashi TAKASAKI
  • Publication number: 20170040232
    Abstract: A technique is provided in which a deviation of a characteristic of a semiconductor device is suppressed from occurring. The technique includes a method of a manufacturing a semiconductor device, including: (a) polishing a first silicon-containing layer formed on a substrate including a convex structure; (b) obtaining a data representing a height distribution of a surface of the first silicon-containing layer after performing the step (a); (c) determining a process condition; and (d) supplying a process gas to form a second silicon-containing layer wherein the process gas is activated such that a concentration of an active species of the process gas at a center portion of the substrate differs from a concentration of an active species at a peripheral portion of the substrate to adjust heights of surfaces of a laminated film according to the process condition.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 9, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Masanori NAKAYAMA, Toshiyuki KIKUCHI, Atsuhiko SUDA, Kazuyuki TOYODA, Shun MATSUI
  • Publication number: 20170040233
    Abstract: Deviation in properties of a semiconductor is suppressed. Provided is a configuration including a receiving member configured to receive data representing a film thickness distribution of a silicon-containing film formed on a substrate, a substrate support where the substrate is placed, a gas supply member configured to supply gases in a manner that a hard mask film having a film thickness distribution different from that of the silicon-containing film is formed on the silicon-containing film to maintain a height of an upper surface of the hard mask film in a predetermined range.
    Type: Application
    Filed: August 31, 2016
    Publication date: February 9, 2017
    Inventors: Naofumi OHASHI, Satoshi TAKANO, Toshiyuki KIKUCHI
  • Patent number: 9559022
    Abstract: A method of manufacturing a semiconductor device, includes: forming a film, wherein the act of forming a film includes: transferring a substrate to a process chamber; supplying a first gas to the substrate; and supplying a second gas to the substrate by converting the second gas to plasma with a first high-frequency wave; and performing an adjustment after the act of forming the film, wherein the act of performing includes: measuring a charging condition of the substrate, setting a second high-frequency wave based on the measured charging condition, supplying a third gas to the substrate by converting the third gas to plasma with the second high-frequency wave, and adjusting the charging condition of the substrate.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 31, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi Takeda, Toshiyuki Kikuchi
  • Publication number: 20160293460
    Abstract: A substrate processing apparatus includes a reception part configured to receive film thickness distribution data of a substrate on which a channel region, an insulating film on the channel region, and a first silicon-containing layer as a portion of a silicon-containing film on the insulating film are formed; a substrate mounting part configured to mount the substrate; and a gas supply part configured to supply a gas to form a second silicon-containing layer as a portion of the silicon-containing film on the first silicon-containing layer to have a film thickness distribution different from a film thickness distribution of the film thickness distribution data, thereby correcting a film thickness of the silicon-containing film.
    Type: Application
    Filed: September 18, 2015
    Publication date: October 6, 2016
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi OHASHI, Satoshi TAKANO, Toshiyuki KIKUCHI
  • Publication number: 20160293498
    Abstract: The present disclosure provides a technique capable of suppressing a deviation in a characteristic of a semiconductor device. There is provided a technique includes: (a) receiving data representing a thickness distribution of a polished silicon-containing layer on a substrate comprising a convex structure whereon the polished silicon-containing layer is formed; (b) calculating, based on the data, a process data for reducing a difference between a thickness of a portion of the polished silicon-containing layer formed at a center portion of the substrate and that of the polished silicon-containing layer formed at a peripheral portion of the substrate; (c) loading the substrate into a process chamber; (d) supplying a process gas to the substrate; and (e) compensating for the difference based on the process data by activating the process gas with a magnetic field having a predetermined strength on the substrate.
    Type: Application
    Filed: December 21, 2015
    Publication date: October 6, 2016
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsuhiko SUDA, Kazuyuki TOYODA, Toshiyuki KIKUCHI
  • Publication number: 20160218012
    Abstract: A fine pattern-forming method includes: a core pattern-forming step of forming a core pattern of a predetermined line width at a substrate surface side; a sidewall-forming step of forming a sidewall on the core pattern formed in the core pattern-forming step; and a core pattern removing step of removing the core pattern in a state where the sidewall is left, by using an etching gas after the sidewall-forming step, and is configured such that, in the core pattern removing step, a film deposited at a substrate back side in the core pattern-forming step is removed in parallel to the removal of the core pattern.
    Type: Application
    Filed: September 29, 2014
    Publication date: July 28, 2016
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi SHIMAMOTO, Toshiyuki KIKUCHI, Jiro YUGAMI, Yoshiro HIROSE, Yuichi WADA, Kenji KANAYAMA, Hiroshi ASHIHARA, Kenji KAMEDA
  • Publication number: 20150187652
    Abstract: A method for producing a composite wafer by using a forming wafer having a monocrystal layer, the method comprising: (a) forming, on the monocrystal layer of the forming wafer, a sacrificial layer and a semiconductor crystal layer sequentially; (b) causing a first front surface that is the front surface of a layer formed on the forming wafer to face a second front surface that is the front surface of the transfer target wafer or of a layer formed on the transfer target wafer and is to contact the first front surface, and bonding the forming wafer and the transfer target wafer; and (c) etching the sacrificial layer, and separating the forming wafer from the transfer target wafer in a state that the semiconductor crystal layer is left on the transfer target wafer, wherein the (a) to the (c) are repeated by using the forming wafer separated in the (c).
    Type: Application
    Filed: January 28, 2015
    Publication date: July 2, 2015
    Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Taketsugu YAMAMOTO, Takeshi AOKI, Tatsuro MAEDA, Eiko MIEDA, Toshiyuki KIKUCHI, Arito OGAWA
  • Publication number: 20150155165
    Abstract: A method of producing a composite wafer including a semiconductor crystal layer, includes forming a sacrificial layer and the semiconductor crystal layer above a semiconductor crystal layer forming wafer in the stated order, etching the semiconductor crystal layer to partially expose the sacrificial layer and dividing the semiconductor crystal layer into a plurality of divided pieces, bonding the semiconductor crystal layer forming wafer and a transfer target wafer made of an inorganic material in such a manner that a first surface of the semiconductor crystal layer forming wafer faces and comes into contact with a second surface of the transfer target wafer, and etching the sacrificial layer to separate the transfer target wafer and the semiconductor crystal layer forming wafer from each other with the semiconductor crystal layer being left on the transfer target wafer.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 4, 2015
    Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Masahiko HATA, Takenori OSADA, Taketsugu YAMAMOTO, Takeshi AOKI, Tetsuji YASUDA, Tatsuro MAEDA, Eiko MIEDA, Hideki TAKAGI, Yuichi KURASHIMA, Yasuo KUNII, Toshiyuki KIKUCHI, Arito OGAWA
  • Publication number: 20130071279
    Abstract: A scroll-type fluid machine (1) in which in which a spiral body (50, 52) and an end plate (8a, 10a) come into sliding contact with each other between fixed and movable scrolls (8, 10) with a chip seal (56, 58), which is provided to the spiral body, intervening therebetween. The spiral body of at least one of the scrolls is provided, in the corner on the end plate side thereof, with a base portion (62) formed of a concave arc face (64), and the chip seal of the other scroll is provided, in the corner of a tip end (56a) thereof, with a fillet (70) that is formed of a first convex arc face (72) that comes into sliding contact with the concave arc face.
    Type: Application
    Filed: May 24, 2011
    Publication date: March 21, 2013
    Inventors: Jiro lizuka, Kiyoshi Terauchi, Shinichi Ohtake, Takayuki Kudo, Toshiyuki Kikuchi
  • Patent number: 7909931
    Abstract: The present invention provides a silica glass crucible for manufacturing a silicon single crystal, in which melt vibration can be controlled more certainly and a high yield of single crystal can be realized. A first substantially bubble-free layer 10a having a thickness of 100 ?m-450 ?m is formed on the inner periphery side of an initial melt line zone 10 which has a height of 10 mm-30 mm, of a transparent layer, a bubble-containing layer 10b having a thickness of 100 ?m or more and bubbles with an average diameter of 20 ?m-60 ?m is formed outside the above-mentioned first substantially bubble-free layer 10a, and a second substantially bubble-free layer 10c having a thickness of 300 ?m or more is formed on the inner periphery side in the whole region lower than the above-mentioned initial melt line zone 10.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: March 22, 2011
    Assignee: Covalent Materials Corporation
    Inventors: Ryouhei Saito, Toshiyuki Kikuchi, Kiyoaki Misu, Kazuko Fukutani, Kazuyoshi Kato
  • Patent number: 7564574
    Abstract: An image forming apparatus of the present invention includes a fixing device for fixing a toner image on a sheet with heat. A main and an auxiliary power supply feed power to the fixing device. A switching circuit selectively establishes a usual mode in which the main power supply is connected to the fixing device or an auxiliary mode in which the main and auxiliary power supplies both are connected to the fixing device. A control circuit causes the switching circuit to establish the auxiliary mode in the event of continuous fixation, controls, in the usual mode, the amount of power fed from the main power supply to the fixing device in accordance with the output of a temperature sensor responsive to the temperature of the fixing device, and controls, in the auxiliary mode, the amount of power fed from the main and auxiliary power supplies to the fixing device without regard to the output of the temperature sensor.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: July 21, 2009
    Assignee: Ricoh Company, Ltd.
    Inventor: Toshiyuki Kikuchi
  • Publication number: 20070256628
    Abstract: The present invention provides a silica glass crucible for manufacturing a silicon single crystal, in which melt vibration can be controlled more certainly and a high yield of single crystal can be realized. A first substantially bubble-free layer 10a having a thickness of 100 ?m-450 ?m is formed on the inner periphery side of an initial melt line zone 10, which has a height of 10 mm-30 mm, of a transparent layer, a bubble-containing layer 10b having a thickness of 100 ?m or more and bubbles with an average diameter of 20 ?m-60 ?m is formed outside the above-mentioned first substantially bubble-free layer 10a, and a second substantially bubble-free layer 10c having a thickness of 300 ?m or more is formed on the inner periphery side in the whole region lower than the above-mentioned initial melt line zone 10.
    Type: Application
    Filed: March 30, 2007
    Publication date: November 8, 2007
    Inventors: Ryouhei Saito, Toshiyuki Kikuchi, Kiyoaki Misu, Kazuko Fukutani, Kazuyoshi Kato
  • Patent number: 7238582
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: July 3, 2007
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Publication number: 20050230716
    Abstract: The object of the present invention is to suppress the increase of the contact resistance at the interface between the metal layer and the silicon plug in the wiring structure in which a metal layer is formed on and connected to a silicon plug. For its achievement, a lower semiconductor layer (drain) of a vertical-type MISFET is connected to an intermediate metal layer via an underlying plug composed of a polycrystalline silicon film, and a trap layer composed of a silicon nitride (TiN) film is formed on a part of the surface of the intermediate metal layer so as to surround the plug. The trap layer is formed in order to prevent an undesired high-resistance oxide layer from being formed at the interface between the plug and the intermediate metal layer.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 20, 2005
    Inventors: Satoshi Moriya, Toshiyuki Kikuchi, Akihiko Konno, Hidenori Sato, Naoki Yamamoto, Masamichi Matsuoka, Hiraku Chakihara, Akio Nishida
  • Patent number: 6941086
    Abstract: A photoreceptor transfers a first image to a first side of a paper, an intermediate transfer belt transfers a second image to a second side of the paper. The intermediate transfer belt also conveys the paper. A conveying unit directly conveys the paper, with the images, to a heating unit that fixes the images. The paper is slowly conveyed in the heating unit as compared to when it is conveyed by the belt.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: September 6, 2005
    Assignee: Ricoh Company., Ltd.
    Inventor: Toshiyuki Kikuchi