Patents by Inventor Troy A. Manning

Troy A. Manning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses and methods for performing compare operations using sensing circuitry
    Patent number: 9466340
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: October 11, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Apparatuses and methods for performing an exclusive or operation using sensing circuitry
    Patent number: 9455020
    Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: September 27, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Hot memory block table in a solid state storage device
    Patent number: 9418017
    Abstract: Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: August 16, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy Manning
  • DUAL EVENT COMMAND
    Publication number: 20160225430
    Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 4, 2016
    Inventors: Joo S. Choi, Troy A. Manning, Brent Keeth
  • Determining a location of a memory device in a solid state device
    Patent number: 9405679
    Abstract: A solid state device has a controller.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: August 2, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy Manning
  • GENERATING AND EXECUTING A CONTROL FLOW
    Publication number: 20160196142
    Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.
    Type: Application
    Filed: December 28, 2015
    Publication date: July 7, 2016
    Inventors: Kyle B. Wheeler, Richard C. Murphy, Troy A. Manning, Dean A. Klein
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20160172015
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Application
    Filed: February 23, 2016
    Publication date: June 16, 2016
    Inventor: Troy A. Manning
  • Dual event command
    Patent number: 9324391
    Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: April 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Joo S. Choi, Troy A. Manning, Brent Keeth
  • Data protection across multiple memory blocks
    Patent number: 9298545
    Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location of the second memory block can be different than the first location of the first memory block.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: March 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sampath K. Ratnam, Troy D. Larsen, Doyle W. Rivers, Troy A. Manning, Martin L. Culley
  • Memory address translation
    Patent number: 9274973
    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: March 1, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Martin L. Culley, Troy D. Larsen
  • Apparatuses and methods for performing logical operations using sensing circuitry
    Patent number: 9275701
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: March 1, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20160027497
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Application
    Filed: October 8, 2015
    Publication date: January 28, 2016
    Inventor: Troy A. Manning
  • DETERMINING A LOCATION OF A MEMORY DEVICE IN A SOLID STATE DEVICE
    Publication number: 20160026564
    Abstract: A solid state device has a controller. The controller is configured to perform a first division operation that divides a received logical block address that indicates a physical memory block in a memory device of a plurality of memory devices in the solid state device by a number of logical block addresses per page of the physical memory block to obtain a result of the first division operation, configured to perform a second division operation that divides the obtained result of the first division operation by a number of memory devices in the plurality of memory devices, and configured to determine a location of the memory device of the plurality of memory devices within the solid state device from a location in a memory device table, the location in the memory device table identified by a remainder of the second division operation.
    Type: Application
    Filed: October 1, 2015
    Publication date: January 28, 2016
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Troy Manning
  • DATA COMPRESSION AND MANAGEMENT
    Publication number: 20160018993
    Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley, Jeffrey L. Meader, Steve G. Bard, Dean C. Eyres
  • INDEPENDENTLY ADDRESSABLE MEMORY ARRAY ADDRESS SPACES
    Publication number: 20160005447
    Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 7, 2016
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PERFORMING AN EXCLUSIVE OR OPERATION USING SENSING CIRCUITRY
    Publication number: 20150357020
    Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.
    Type: Application
    Filed: May 18, 2015
    Publication date: December 10, 2015
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY
    Publication number: 20150357007
    Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.
    Type: Application
    Filed: May 15, 2015
    Publication date: December 10, 2015
    Inventors: Troy A. Manning, Richard C. Murphy
  • COMPARISON OPERATIONS IN MEMORY
    Publication number: 20150357019
    Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
    Type: Application
    Filed: May 18, 2015
    Publication date: December 10, 2015
    Inventors: Kyle B. Wheeler, Troy A. Manning, Richard C. Murphy
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20150357024
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 10, 2015
    Inventors: Glen E. Hush, Troy A. Manning
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20150357008
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a compute component. The sensing circuitry is configured to invert a data value in the compute component.
    Type: Application
    Filed: May 28, 2015
    Publication date: December 10, 2015
    Inventors: Troy A. Manning, Richard C. Murphy