Patents by Inventor Troy A. Manning

Troy A. Manning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20150029798
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 29, 2015
    Applicant: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE
    Publication number: 20140365720
    Abstract: Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.
    Type: Application
    Filed: August 25, 2014
    Publication date: December 11, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Troy Manning
  • Memory address translation
    Patent number: 8898424
    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Martin L. Culley, Troy D. Larsen
  • DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS
    Publication number: 20140325316
    Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 30, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Sampath K. Ratnam, Troy D. Larsen, Doyle W. Rivers, Troy A. Manning, Martin L. Culley
  • LOGICAL ADDRESS TRANSLATION
    Publication number: 20140317374
    Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 23, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Martin L. Culley, Troy A. Manning, Troy D. Larsen
  • DATA RECOVERY IN A SOLID STATE STORAGE SYSTEM
    Publication number: 20140298090
    Abstract: Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.
    Type: Application
    Filed: May 15, 2014
    Publication date: October 2, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Troy Larsen, Martin Culley, Troy Manning
  • MEMORY ADDRESS TRANSLATION
    Publication number: 20140297990
    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
    Type: Application
    Filed: May 5, 2014
    Publication date: October 2, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Troy A. Manning, Martin L. Culley, Troy D. Larsen
  • Translation layer in a solid state storage device
    Patent number: 8838876
    Abstract: Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: September 16, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Troy Manning
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20140250279
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 4, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Troy A. Manning
  • LOGICAL UNIT OPERATION
    Publication number: 20140250261
    Abstract: The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 4, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • HOT MEMORY BLOCK TABLE IN A SOLID STATE STORAGE DEVICE
    Publication number: 20140237169
    Abstract: Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 21, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Troy Manning
  • Stacked device remapping and repair
    Patent number: 8787101
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Logical unit operation
    Patent number: 8762621
    Abstract: The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Memory address translation
    Patent number: 8756400
    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Martin L. Culley, Troy D. Larsen
  • TEMPORARY MIRRORING, LOGICAL SEGREGATION, AND REDUNDANT PROGRAMMING OR ADDRESSING FOR SOLID STATE DRIVE OPERATION
    Publication number: 20140143479
    Abstract: The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event.
    Type: Application
    Filed: October 15, 2013
    Publication date: May 22, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Data recovery in a solid state storage system
    Patent number: 8732549
    Abstract: Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Larsen Troy, Martin Culley, Troy Manning
  • Logical address translation
    Patent number: 8732431
    Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
    Type: Grant
    Filed: March 6, 2011
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Martin L. Culley, Troy A. Manning, Troy D. Larsen
  • Data protection across multiple memory blocks
    Patent number: 8732557
    Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first memory block and writing a second portion of the codeword in a second memory block. The first memory block and the second memory block can be different memory blocks. The first portion of the codeword can be written in a different location in the first memory block than the second portion of the codeword is written in the second memory block.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Sampath K. Ratnam, Troy D. Larsen, Doyle W. Rivers, Troy A. Manning, Martin L. Culley
  • Hot memory block table in a solid state storage device
    Patent number: 8725927
    Abstract: Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Troy Manning
  • METHOD FOR COATING SUBSTRATES
    Publication number: 20140044977
    Abstract: A method for coating a substrate with a coating having a controlled morphology is disclosed, the method comprising providing a substrate, depositing a nucleating layer on a surface of the substrate using an aerosol assisted deposition method and depositing at least one further layer by chemical vapour deposition. The nucleating layer and further layer preferably comprise tin oxide. The substrate is preferably glass. The method results in high transmittance and a low diffuse transmission across the visible and infrared region.
    Type: Application
    Filed: April 17, 2012
    Publication date: February 13, 2014
    Applicants: UNIVERSITY COLLEGE LONDON, PILKINGTON GROUP LIMITED
    Inventors: Troy Manning, Ivan Paul Parkin, Mathew Robert Waugh