Patents by Inventor Troy A. Manning

Troy A. Manning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20170365301
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Application
    Filed: August 31, 2017
    Publication date: December 21, 2017
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20170358332
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 14, 2017
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PARALLEL WRITING TO MULTIPLE MEMORY DEVICE STRUCTURES
    Publication number: 20170336989
    Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.
    Type: Application
    Filed: August 4, 2017
    Publication date: November 23, 2017
    Inventors: Jason T. Zawodny, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner
  • Apparatuses and methods for performing compare operations using sensing circuitry
    Patent number: 9799378
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: October 24, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY
    Publication number: 20170301377
    Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 19, 2017
    Inventors: Troy A. Manning, Richard C. Murphy
  • Apparatuses and methods for performing logical operations using sensing circuitry
    Patent number: 9786335
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 10, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Troy A. Manning
  • Memory command received within two clock cycles
    Patent number: 9767886
    Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Joo S Choi, Troy A. Manning, Brent Keeth
  • Apparatuses and methods for performing compare operations using sensing circuitry
    Patent number: 9767865
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Apparatuses and methods for parity determination using sensing circuitry
    Patent number: 9704540
    Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: July 11, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Richard C. Murphy
  • Data compression and management
    Patent number: 9696910
    Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley, Jeffrey L. Meader, Steve G. Bard, Dean C. Eyres
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20170162243
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventor: Troy A. Manning
  • Apparatuses and methods for performing logical operations using sensing circuitry
    Patent number: 9589607
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: March 7, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • COMPARISON OPERATIONS IN MEMORY
    Publication number: 20170053693
    Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
    Type: Application
    Filed: November 8, 2016
    Publication date: February 23, 2017
    Inventors: Kyle B. Wheeler, Troy A. Manning, Richard C. Murphy
  • APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20170025160
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Application
    Filed: October 7, 2016
    Publication date: January 26, 2017
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20170011782
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventor: Troy A. Manning
  • Independently addressable memory array address spaces
    Patent number: 9530475
    Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 27, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PERFORMING AN EXCLUSIVE OR OPERATION USING SENSING CIRCUITRY
    Publication number: 20160372177
    Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventor: Troy A. Manning
  • Comparison operations on logical representations of values in memory
    Patent number: 9496023
    Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: November 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Wheeler, Troy A. Manning, Richard C. Murphy
  • Temporary mirroring, logical segregation, and redundant programming or addressing for solid state drive operation
    Patent number: 9483203
    Abstract: The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: November 1, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Apparatuses and methods for performing logical operations using sensing circuitry
    Patent number: 9472265
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: October 18, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning