Patents by Inventor Troy A. Manning

Troy A. Manning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data recovery in a solid state storage system
    Patent number: 9201718
    Abstract: Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 1, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Troy Larsen, Martin Culley, Troy Manning
  • Translation layer in a solid state storage device
    Patent number: 9176868
    Abstract: Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: November 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy Manning
  • Logical address translation
    Patent number: 9164701
    Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Martin L. Culley, Troy A. Manning, Troy D. Larsen
  • Apparatuses and methods for performing logical operations using sensing circuitry
    Patent number: 9158667
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Independently addressable memory array address spaces
    Patent number: 9153305
    Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 6, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR COMPARING DATA PATTERNS IN MEMORY
    Publication number: 20150279466
    Abstract: The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventor: Troy A. Manning
  • Data compression and management
    Patent number: 9148172
    Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: September 29, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley, Jeffrey L. Meader, Steve G. Bard, Dean C. Eyres
  • MEMORY MAPPING
    Publication number: 20150270015
    Abstract: The present disclosure includes apparatuses, electronic device readable media, and methods for memory mapping. One example method can include testing a memory identifier against an indication corresponding to a set of mapped memory identifiers, and determining a memory location corresponding to the memory identifier responsive to testing.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Troy A. Manning
  • Logical unit operation
    Patent number: 9128637
    Abstract: The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: September 8, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • PHYSICAL PAGE, LOGICAL PAGE, AND CODEWORD CORRESPONDENCE
    Publication number: 20150212882
    Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
    Type: Application
    Filed: April 8, 2015
    Publication date: July 30, 2015
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley
  • Logical unit operation
    Patent number: 9052842
    Abstract: The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 9, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE
    Publication number: 20150149712
    Abstract: Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.
    Type: Application
    Filed: February 5, 2015
    Publication date: May 28, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Troy Manning
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20150138896
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Inventor: Troy A. Manning
  • APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20150131390
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventor: Troy A. Manning
  • Physical page, logical page, and codeword correspondence
    Patent number: 9026887
    Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 5, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley
  • INDEPENDENTLY ADDRESSABLE MEMORY ARRAY ADDRESS SPACES
    Publication number: 20150063052
    Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Apparatuses and methods for performing logical operations using sensing circuitry
    Patent number: 8971124
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Apparatuses and methods for performing compare operations using sensing circuitry
    Patent number: 8964496
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Translation layer in a solid state storage device
    Patent number: 8966165
    Abstract: Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy Manning
  • APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    Publication number: 20150042380
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 12, 2015
    Applicant: Micron Technology, Inc.
    Inventor: Troy A. Manning