Patents by Inventor Tsai-An Yu

Tsai-An Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9030015
    Abstract: A 3-D chip stacked structure is disclosed. Each chip layer is provided with plural single-layered conductive members where among the same chip layer the two adjacent conductive members are structurally formed in mirror symmetric way with each other along a chip longitudinal direction and the arrangements of the single-layered conductive members of the two adjacent chip layers are shifted by a test pad distance. The single-layered conductive members of the two adjacent chip layers are communicated through a vertical TSV (through silicon via). Therefore, a selection signal or an enabling signal might be transferred through this specific metal layer and related TSV to reach targeting chip layer and targeting circuit.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: May 12, 2015
    Inventors: Tsai-Yu Huang, Yi-Feng Huang
  • Patent number: 9012324
    Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
  • Publication number: 20150093874
    Abstract: Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material.
    Type: Application
    Filed: December 5, 2014
    Publication date: April 2, 2015
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
  • Patent number: 8940333
    Abstract: An amphiphilic block copolymer is disclosed. The amphiphilic block copolymer includes one or more hydrophilic polymers, one or more hydrophobic polymer, and one or more zwitterions. The invention also provides a nanoparticle and carrier including the amphiphilic block copolymer for delivery of water insoluble drugs, growth factors, genes, or water insoluble cosmetic substances.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: January 27, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Fa Hsieh, Hsuen-Tseng Cha'ng, Chin-Fu Chen, Yuan-Chia Chang, Pei Kan, Tsai-Yu Lin
  • Patent number: 8936991
    Abstract: Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: January 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
  • Patent number: 8927441
    Abstract: Methods of forming rutile titanium dioxide comprise exposing a transition metal (such as V, Cr, W, Mn, Ru, Os, Rh, Ir, Pt, Ge, Sn, or Pb) to an atmosphere consisting of oxygen gas (O2) to produce an oxidized transition metal over an unoxidized portion of the transition metal. Rutile titanium dioxide is formed over the oxidized transition metal by atomic layer deposition. The oxidized transition metal is sequentially exposed to a titanium halide precursor and an oxidizer. Other methods include oxidizing a portion of a ruthenium material to ruthenium(IV) oxide using an atmosphere consisting of O2, nitric oxide (NO), or nitrous oxide (N2O); and introducing a gaseous titanium halide precursor and water vapor to the ruthenium(IV) oxide to form rutile titanium dioxide on the ruthenium(IV) oxide by atomic layer deposition. Some methods include exposing transition metal to an atmosphere consisting essentially of O2, NO, and N2O.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chris Carlson
  • Patent number: 8866281
    Abstract: A three-dimensional integrated circuit is disclosed, including a first interposer including through substrate vias (TSV) therein and circuits thereon; a plurality of first active dies disposed on a first side of the first interposer, a plurality of first intermediate interposers, each including through substrate vias (TSV), disposed on the first side of the first interposer, and a second interposer including through substrate vias (TSV) therein and circuits thereon supported by the first intermediate interposers.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: October 21, 2014
    Assignee: Nanya Technology Corporation
    Inventor: Tsai-Yu Huang
  • Patent number: 8853060
    Abstract: An epitaxial process includes the following step. A recess is formed in a substrate. A seeding layer is formed to cover a surface of the recess. A buffer layer is formed on the seeding layer. An etching process is performed on the buffer layer to homogenize and shape the buffer layer. An epitaxial layer is formed on the homogenized flat bottom shape buffer layer.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Szu-Hao Lai, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Ming-Hua Chang, Yu-Shu Lin, Tsai-Yu Wen, Hsin-Kuo Hsu
  • Publication number: 20140295629
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 2, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
  • Publication number: 20140210049
    Abstract: Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material.
    Type: Application
    Filed: April 3, 2014
    Publication date: July 31, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
  • Publication number: 20140191234
    Abstract: A 3-D chip stacked structure is disclosed. Each chip layer is provided with plural single-layered conductive members where among the same chip layer the two adjacent conductive members are structurally formed in minor symmetric way with each other along a chip longitudinal direction and the arrangements of the single-layered conductive members of the two adjacent chip layers are shifted by a test pad distance. The single-layered conductive members of the two adjacent chip layers are communicated through a vertical TSV (through silicon via). Therefore, a selection signal or an enabling signal might be transferred through this specific metal layer and related TSV to reach targeting chip layer and targeting circuit.
    Type: Application
    Filed: January 3, 2014
    Publication date: July 10, 2014
    Inventors: Tsai-Yu Huang, Yi-Feng Huang
  • Publication number: 20140162431
    Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.
    Type: Application
    Filed: December 11, 2012
    Publication date: June 12, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Keng-Jen Lin, Yu-Ren Wang, Chih-Chung Chen, Tsuo-Wen Lu, Tsai-Yu Wen
  • Patent number: 8748283
    Abstract: Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
  • Patent number: 8697508
    Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. An oxide layer is formed and covers the gate structure and the substrate. A plasma process without oxygen is performed to densify the oxide layer. A material layer is formed and covers the oxide layer. The material layer and the oxide layer are etched to form a dual spacer.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: April 15, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20140065301
    Abstract: Methods of forming rutile titanium dioxide comprise exposing a transition metal (such as V, Cr, W, Mn, Ru, Os, Rh, Ir, Pt, Ge, Sn, or Pb) to an atmosphere consisting of oxygen gas (O2) to produce an oxidized transition metal over an unoxidized portion of the transition metal. Rutile titanium dioxide is formed over the oxidized transition metal by atomic layer deposition. The oxidized transition metal is sequentially exposed to a titanium halide precursor and an oxidizer. Other methods include oxidizing a portion of a ruthenium material to ruthenium(IV) oxide using an atmosphere consisting of O2, nitric oxide (NO), or nitrous oxide (N2O); and introducing a gaseous titanium halide precursor and water vapor to the ruthenium(IV) oxide to form rutile titanium dioxide on the ruthenium(IV) oxide by atomic layer deposition. Some methods include exposing transition metal to an atmosphere consisting essentially of O2, NO, and N2O.
    Type: Application
    Filed: November 13, 2013
    Publication date: March 6, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chris Carlson
  • Publication number: 20140057434
    Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
  • Publication number: 20140021599
    Abstract: A three-dimensional integrated circuit is disclosed, including a first interposer including through substrate vias (TSV) therein and circuits thereon; a plurality of first active dies disposed on a first side of the first interposer, a plurality of first intermediate interposers, each including through substrate vias (TSV), disposed on the first side of the first interposer, and a second interposer including through substrate vias (TSV) therein and circuits thereon supported by the first intermediate interposers.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Tsai-Yu Huang
  • Patent number: 8614190
    Abstract: Thermal responsive compositions for treating bone diseases are provided. The thermal responsive composition for treating bone diseases includes a bone growth factor and a biodegradable copolymer. The biodegradable copolymer has a structure of Formula (I) or Formula (II): A-B-BOX-B-A??Formula (I) B-A-B-(BOX-B-A-B)n-BOX-B-A-B??Formula (II) wherein, A includes a hydrophilic polyethylene glycol polymer, B includes a hydrophobic polyester polymer, BOX is a bifunctional group monomer of 2, 2?-Bis(2-oxazoline) and used for coupling the blocks A-B or B-A-B, and n is an integer and the same or more than 0.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: December 24, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Shen-Hua Peng, Hsin-Hsin Shen, Liang-Yo Yang, Meng-Yow Hsieh, Pei-Shan Li, Wei-Lin Yu, Tsai-Yu Lin, Po-Liang Lai, Jui-Sheng Sun, Chih-Hung Chang, Yi-Hung Lin
  • Patent number: 8609553
    Abstract: Methods of forming rutile titanium dioxide. The method comprises exposing a transition metal (such as V, Cr, W, Mn, Ru, Os, Rh, Ir, Pt, Ge, Sn, or Pb) to oxygen gas (O2) to oxidize the transition metal. Rutile titanium dioxide is formed over the oxidized transition metal. The rutile titanium dioxide is formed by atomic layer deposition by introducing a gaseous titanium halide precursor and water to the oxidized transition metal. Methods of forming semiconductor structures having rutile titanium dioxide are also disclosed.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chris Carlson
  • Publication number: 20130322653
    Abstract: A USB audio device includes a USB connector for connection to a general purpose computer, a USB controller connected to the USB connector for receiving an digitized audio signal from the computer and transmitting a digitized microphone signal and a controlling signal to the computer system, a digital/analog converter connected to the USB controller for processing the audio signal and the microphone signal and an earset socket connected to the digital/analog converter and having a left signal contact, a right signal contact, a ground contact, and a microphone signal contact.
    Type: Application
    Filed: August 1, 2012
    Publication date: December 5, 2013
    Applicant: FORMOSA21 Inc.
    Inventors: TSAI Yu-Fen, Chang Jung-Chin, Tu Randy, Lin Shar-Ming