Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.

Abstract: An electronic device including a main body, a handle and a driven mechanism is provided. The main body includes a base and a button unit movably disposed on the base. The handle is movably connected to the main body. The handle is adapted to be rotated from a first position to a second position relative to the main body. The driven mechanism includes a first connection element and an ascending/descending assembly. A first section of the first connection element is fixed to the handle, and a second section of the first connection element is movably disposed in the base. The ascending/descending assembly is disposed in the base and located between the second section and a bottom of the button unit. When the handle is rotated from the first position to the second position, the first connection element moves with the handle, and the ascending/descending assembly is moved with the second section and lifts up the button unit.

Abstract: A mattress, bed, cushion, or other device to support a user in a pre-determined posture. The mattress, bed, cushion, or other device includes compressible cells configured to inflate based on characteristics of particular contact areas of the user, and contact, in response to inflating based on the characteristics, the user in various contact areas to support the pre-determined posture. In particular, inflating the compressible cells based on characteristics of particular contact areas reduces the risk of the user developing pressure ulcers.

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

Abstract: A mattress for patient care. The mattress includes a number of compressible cells and a number of sensors corresponding to the number of compressible cells. Each compressible cell is configured to contact, when inflated, a user in a contact area of a plurality of contact areas of the user. Each sensor is configured to generate a number of measurements, wherein each measurement relates to the contact area of a corresponding compressible cell. Each sensor is further configured to send the number of measurements to a pressure control device.

Abstract: A light source board includes a substrate; a metal reactive layer disposed on the substrate; a metal conductive layer disposed on the metal reactive layer; a metal alloy layer disposed on the metal conductive layer; and at least one light source disposed on the metal alloy layer. A material of the metal reactive layer is a Sn—Bi type alloy or a Sn—Ag—Cu type alloy, and arrangements of materials of the metal reactive layer and the metal conductive layer are respectively an arrangement of silver paste and copper, an arrangement of silver paste and nickel, an arrangement of silver paste and silver, an arrangement of copper paste and copper, an arrangement of copper paste and nickel, or an arrangement of copper paste and silver.

Abstract: An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.

Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.

Abstract: A light source board includes a substrate, a composite circuit layer on the substrate, a first protective layer on the composite circuit layer, and a plurality of light sources on the pad portions, respectively. The substrate has a long side, a first short side, and a second short side. The composite circuit layer includes a first conductive trace layer and a second conductive trace layer stacked on the first conductive trace layer. A conductivity of the second conductive trace layer is higher than a conductivity of the first conductive trace layer. The composite circuit layer has a wire portion formed of at least the first conductive trace layer and a plurality of pad portions each formed of at least the first conductive trace layer and the second conductive trace layer. The wire portion is electrically coupled to the pad portions. The first protective layer exposes the pad portions.

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

Abstract: A light emitting keyboard includes a bottom board, keyswitches, and a lighting board. The lighting board is disposed between the bottom board and the keyswitches or under the bottom board and includes a flexible substrate having a first hole, multiple-light emitting diodes corresponding to the keyswitches, first and second silver-paste circuit layers formed on upper and lower surfaces of the flexible substrate respectively, a via pillar formed in the first hole to be coupled to the first and second silver-paste circuit layers, a copper layer plated on the first and second silver-paste circuit layers, and a first protection layer coated on the copper layer and having second holes. Each multiple-light emitting diode is disposed on the copper layer plated on the first silver-paste circuit layer through the corresponding second hole to be coupled to the first silver-paste circuit layer.

Abstract: A set of test key layout including multiple test keys and method of monitoring layout pattern misalignments using the test keys is provided. Each test key is composed of a testing electrode, an operating voltage (Vdd) line and a grounding voltage (Vss) line, wherein the patterns of test keys are defined by an overlapped portion of a first exposure pattern and a second exposure pattern, and the position of testing electrode is shifted sequentially in one direction in order of the test keys.

Abstract: A light source board includes a substrate, a composite circuit layer on the substrate, a first protective layer on the composite circuit layer, and a plurality of light sources on the pad portions, respectively. The substrate has a long side, a first short side, and a second short side. The composite circuit layer includes a first conductive trace layer and a second conductive trace layer stacked on the first conductive trace layer. A conductivity of the second conductive trace layer is higher than a conductivity of the first conductive trace layer. The composite circuit layer has a wire portion formed of at least the first conductive trace layer and a plurality of pad portions each formed of at least the first conductive trace layer and the second conductive trace layer. The wire portion is electrically coupled to the pad portions. The first protective layer exposes the pad portions.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

Abstract: An expansion module is detachably assembled with a portable computer. The expansion module includes a plate member, a supporting plate, a deformable connecting member, and an expansion unit. The supporting plate is pivoted to the plate member to rotate relative to the plate member between an opened position and a closed position. When the supporting plate is in the closed position, the supporting plate and the plate member defines an accommodating space. The deformable connecting member is connected to the plate member. The expansion unit is connected to the plate member through the deformable connecting member. When the supporting plate is in the closed position, the expansion unit is rotated from a first position to a second position by bending the deformable connecting member and is stored in the accommodating space.

Abstract: A paper straw has an inner tube, an outer tube, and a pattern portion. The inner tube and the outer tube are both tubular bodies formed by spirally winding paper sheets. The pattern portion is disposed between the inner tube and the outer tube. The paper sheets that are used to wind the inner tube and the outer tube have light-transmissive properties. Then the pattern portion can be externally displayed through the outer tube or the inner tube, and this can avoid the pattern portion directly contacting food or human body.

Abstract: An ultra-thin broadband retardation film is provided. The broadband retardation film includes a first retardation film and a second retardation film. The second retardation film is disposed on a side of the first retardation film, wherein an in-plane retardation value Ro of the first retardation film is between 70 nm and 130 nm, an in-plane retardation value Ro of the second retardation film is between 140 nm and 260 nm, and an angle between an optic axis of the first retardation film and an optic axis of the second retardation film is between 35° and 70°.

Abstract: A display device is provided. The display device includes an organic light emitting diode display panel, a blue light brightness enhancement film and a polarizing film. The blue light brightness enhancement film is disposed on the organic light emitting diode display panel. The blue light brightness enhancement film includes a cholesteric liquid crystal layer and a quarter-wave phase retardation film, and the quarter-wave phase retardation film is disposed on the cholesteric liquid crystal layer. The polarizing film is disposed on the blue light brightness enhancement film.