Patents by Inventor Tsai-An Yu

Tsai-An Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9653549
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Publication number: 20170106125
    Abstract: The present disclosure provides a hydrogel composition including: a hydrogel having a structure represented by Formula (I) or Formula (II) shown as follows: A-B-BOX-B-A, Formula (I); B-A-B-(BOX-BAB)n-BOX-B-A-B, Formula (II), wherein, A is a hydrophilic polyethylene glycol polymer, B is a hydrophobic polyester polymer, BOX is a bifunctional group monomer of 2,2?-Bis(2-oxazoline) for coupling di-block of A-B or tri-block of B-A-B, and n is an integer greater than or equal to 0; and an anti-adhesion additive, wherein the anti-adhesion additive comprises a carbohydrate, a nitrogen-containing cyclic compound, a polymer or a combination thereof.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Chi WANG, Hsin-Hsin SHEN, Chin-Fu CHEN, Meng-Yow HSIEH, Sen-Lu CHEN, Yu-Bing LIOU, Tsai-Yu LIN, Pei-Shan LI, Wei-Lin YU
  • Publication number: 20160329400
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160282909
    Abstract: An electronic apparatus includes a base and an electronic device. The base includes a first main body and at least one first connection portion. The first connection portion includes a rotating component, and the rotating component is pivoted to the first main body and has a driven portion and a positioning portion. The electronic device includes a second main body and at least one second connection portion. The second connection portion includes an elastic component and a positioning trench. The elastic component is connected to the second main body, and the positioning trench is formed on the second main body. When the base supports the electronic device so that the first connection portion is aligned to the second connection portion, the elastic component pushes the driven portion such that the positioning portion is engaged into the positioning trench.
    Type: Application
    Filed: January 19, 2016
    Publication date: September 29, 2016
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Jyh-Chyang Tzou, Hsin Yeh, Chia-Shin Weng, Wei-Hao Lan, Tsai-Yu Lin, Yuan-Ping Chu
  • Publication number: 20160276431
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160276434
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Patent number: 9431483
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160234868
    Abstract: Systems and methods are disclosed for security monitoring using a mobile device by detecting an activation condition associated with an emergency; and capturing and sending emergency data stream including images or video, audio, and positioning coordinates to a cloud-based processor to store and forward to a predetermined circle of family and friends to allow them to view the stream of audio, images/video and positioning coordinates in real time.
    Type: Application
    Filed: December 1, 2015
    Publication date: August 11, 2016
    Inventors: Noor Gill, Tsai-Yu Lam, Vincent Viricel, Michael Zideah
  • Patent number: 9379182
    Abstract: A method for forming germanium nanowires comprises forming a semiconductor fin structure including alternating fin and shallow trench structures, etching a top portion of the fin to form a fin recess and depositing a germanium-based semiconductor into the fin recess as a germanium-based plug. The method comprises etching the shallow trench structure to expose the germanium-based semiconductor side faces. The exposed germanium-based semiconductor undergoes annealing to form high carrier mobility nanowire structures. The nanowire structures can also be formed of different diameters by selective oxidation of some of the deposited germanium-based plugs. Alternately, forming fin structures of different widths results in deposited germanium plugs of different widths to be deposited to form different thicknesses of nanowires.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Patent number: 9349599
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160133474
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 12, 2016
    Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9330902
    Abstract: A method for forming a HfOx film based on atomic layer deposition (ALD) process includes: providing a substrate; dividing a plurality of ALD cycles as needed into multiple depositing stages, wherein each of the ALD cycles includes applying HfCl4 pulse and applying H2O pulse over the substrate and a content ratio of HfCl4 to H2O is different and increasing for the depositing stages; and performing the depositing stages to form a HfOx film.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 3, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Shih-Cheng Chen, Shan Ye, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160056038
    Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.
    Type: Application
    Filed: October 30, 2015
    Publication date: February 25, 2016
    Inventors: Nik Mirin, Tsai-Yu Huang, Vishwanath Bhat, Chris M. Carlson, Vassil N. Antonov
  • Patent number: 9209013
    Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: December 8, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Nik Mirin, Tsai-Yu Huang, Vishwanath Bhat, Chris M. Carlson, Vassil N. Antonov
  • Patent number: 9159731
    Abstract: Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
  • Patent number: 9117878
    Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: August 25, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Keng-Jen Lin, Yu-Ren Wang, Chih-Chung Chen, Tsuo-Wen Lu, Tsai-Yu Wen
  • Publication number: 20150162510
    Abstract: A light emitting diode module includes a lead frame, a first light emitting diode chip, a second light emitting diode chip, an encapsulant, and a lens structure. The lead frame has a die-bonding surface and a side wall together defining an accommodating recess. The encapsulant is filled in the accommodating recess, and covers the first and the second light emitting diode chips. The lens structure disposed on the lead frame has a bottom surface, a reflective surface, a first, a second, a third, and a fourth light emitting curved surface. The light emitting curved surfaces are respectively disposed opposite to the bottom surface. An adjacent position among the light emitting curved surfaces is a lowest point nearest to the bottom surface. The first and the second light emitting diode chips are disposed at the projections of the first and the second light emitting curved surface on the die-bonding surface.
    Type: Application
    Filed: April 20, 2014
    Publication date: June 11, 2015
    Applicant: Lextar Electronics Corporation
    Inventors: Tsai-Yu CHEN, Chun-Wei Wang
  • Patent number: 9054286
    Abstract: A light emitting diode module includes a lead frame, a first light emitting diode chip, a second light emitting diode chip, an encapsulant, and a lens structure. The lead frame has a die-bonding surface and a side wall together defining an accommodating recess. The encapsulant is filled in the accommodating recess, and covers the first and the second light emitting diode chips. The lens structure disposed on the lead frame has a bottom surface, a reflective surface, a first, a second, a third, and a fourth light emitting curved surface. The light emitting curved surfaces are respectively disposed opposite to the bottom surface. An adjacent position among the light emitting curved surfaces is a lowest point nearest to the bottom surface. The first and the second light emitting diode chips are disposed at the projections of the first and the second light emitting curved surface on the die-bonding surface.
    Type: Grant
    Filed: April 20, 2014
    Date of Patent: June 9, 2015
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Tsai-Yu Chen, Chun-Wei Wang
  • Patent number: 9034705
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 19, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
  • Patent number: D756012
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: May 10, 2016
    Assignee: HELLA KGAA HUECK & CO.
    Inventor: Tsai Yu Shu